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KS57C2302/C2304/P2304 MICROCONTROLLER
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The KS57C2302/C2304 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the KS57C2302/C2304 offers an excellent design solution for a wide variety of applications that require LCD functions. Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast response to internal and external events. In addition, the KS57C2302/C2304 's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The KS57C2302/C2304 microcontroller is also available in OTP (One Time Programmable) version, KS57P2304 . The KS57P2304 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The KS57P2304 is comparable to KS57C2302/C2304, both in function and in pin configuration.
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PRODUCT OVERVIEW
KS57C2302/C2304/P2304 MICROCONTROLLER
FEATURES
Memory -- 288 x 4-bit RAM -- 2048 x 8-bit ROM (KS57C2302) -- 4096 x 8-bit ROM (KS57C2304) I/O Pins -- Input only: 4 pins -- I/O: 12 pins -- Output: 8 pins sharing with segment driver outputs LCD Controller/Driver -- Maximum 16-digit LCD direct drive capability -- 32 segment, 4 common pins -- Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-Bit Basic Timer -- Programmable interval timer -- Watchdog timer 8-Bit Timer/Counter -- Programmable 8-bit timer -- External event counter -- Arbitrary clock frequency output Watch Timer -- Real-time and interval time measurement -- Four frequency outputs to BUZ pin -- Clock source generation for LCD Bit Sequential Carrier -- Support 16-bit serial data transfer in arbitrary format Package Type -- 64-pin QFP Oscillation Sources -- Crystal, ceramic, or RC for main system clock -- Crystal or external oscillator for subsystem clock -- Main system clock frequency: 4.19 MHz (typical) -- Subsystem clock frequency: 32.768 kHz -- CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times -- 0.95, 1.91, 15.3 s at 4.19 MHz (main) -- 122 s at 32.768 kHz (subsystem) Operating Temperature -- - 40 C to 85 C Operating Voltage Range -- 2.0 V to 5.5 V at 4.19 MHz -- 1.8 V to 5.5 V at 3 MHz Interrupts -- Two internal vectored interrupts -- Two external vectored interrupts -- Two quasi-interrupts Memory-Mapped I/O Structure -- Data memory bank 15 Two Power-Down Modes -- Idle mode (only CPU clock stops) -- Stop mode (main or sub system oscillation stops)
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KS57C2302/C2304/P2304 MICROCONTROLLER
PRODUCT OVERVIEW
BLOCK DIAGRAM
BASIC TIMER INT0, INT1,INT2
RESET
WATCH TIMER
P2.3/BUZ
Xin XTin
Xout XTout
P1.3/TCL0 P2.0/TCLO0
8-BIT TIMER/ COUNTER 0
INTERRUPT CONTROL BLOCK
CLOCK
INSTRUCTION REGISTER LCD DRIVER/ CONTROLLER
P6.0-P6.3 / KS0-KS3
I/O PORT 6
INTERNAL INTERRUPTS INSTRUCTION DECODER ARITHMETIC AND LOGIC UNIT
PROGRAM COUNTER
BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23 P8.0-P8.7/ SEG24-SEG31
PROGRAM STATUS WORD INPUT PORT 1 STACK POINTER I/O PORT 2
P8.0-P8.7 SEG24-SEG31
OUTPUT PORT 8
P1.0 / INT0 P1.1 / INT1 P1.2 / INT2 P1.3 / TCL0 P2.0 / TCLO0 P2.1 P2.2 / CLO P2.3 / BUZ P3.0 / LCDCK P3.1 / LCDSY P3.2 P3.3
288 x 4-BIT DATA MEMORY
2/4 K BYTE PROGRAM MEMORY
I/O PORT 3
Figure 1-1. KS57C2302/C2304 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C2302/C2304/P2304 MICROCONTROLLER
PIN ASSIGNMENTS
COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS Xout Xin TEST XTin XTout
RESET
P1.0/INT0 P1.1/INT1 P1.2/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12
KS57C2302 KS57C2304
(TOP VIEW)
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 / P8.0 SEG25 / P8.1 SEG26 / P8.2 SEG27 / P8.3 SEG28 / P8.4 SEG29 / P8.5 SEG30 / P8.6 SEG31 / P8.7
Figure 1-2. KS57C2302/C2304 64-QFP Pin Assignment
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P1.3 / TCL0 P2.0 / TCLO0 P2.1 P2.2 / CLO P2.3 / BUZ P3.0 / LCDCK P3.1 / LCDSY P3.2 P3.3 P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / KS3
20 21 22 23 24 25 26 27 28 29 30 31 32
KS57C2302/C2304/P2304 MICROCONTROLLER
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C2302/C2304 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 Pin Type I Description 4-bit input port. 1-bit or 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 4-bit I/O ports. Pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. Output port for 1-bit data (for use as CMOS driver only) LCD segment signal output LCD segment signal output LCD common signal output LCD power supply. Built-in voltage dividing resistors LCD power control LCD clock output for display expansion Number 17 18 19 20 21 22 23 24 25 26 27 28 Share Pin INT0 INT1 INT2 TCL0 TCLO0 - CLO BUZ LCDCK LCDSY Reset Value Input Circuit Type A-4
I/O
Input
D
I/O
Input
D
P6.0-P6.3
I/O
29-32
KS0-KS3
Input
D
P8.0-P8.7 SEG0-SEG23 SEG24-SEG31 COM0-COM3 VLC0-VLC2 BIAS LCDCK
O O O O - - I/O
40-33 64-41 40-33 1-4 6-8 5 25
SEG24- SEG31 - P8.0-P8.7 - - - P3.0
Output Output Output Output - - Input
H-1 H H-1 H - - D
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PRODUCT OVERVIEW
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 1-1. KS57P2304 Pin Descriptions (Continued) Pin Name LCDSY TCL0 TCLO0 INT0 INT1 Pin Type I/O I I/O I Description LCD synchronization clock output for LCD display expansion External clock input for timer/counter 0 Timer/counter 0 clock output External interrupt. The triggering edge for INT0 and INT1 is selectable. Only INT0 is synchronized with the system clock. Quasi-interrupt with detection of rising edge signals. Quasi-interrupt input with falling edge detection. CPU clock output 2, 4, 8 or 16 kHz frequency output for buzzer sound with 4.19 MHz main system clock or 32.768 kHz subsystem clock. Crystal, ceramic or RC oscillator pins for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Crystal oscillator pins for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) Main power supply Ground Reset signal Test signal input (must be connected to VSS) Number 26 20 21 17 18 Share Pin P3.1 P1.3 P2.0 P1.0 P1.1 Reset Value Input Input Input Input Circuit Type D A-4 D A-4
INT2 KS0-KS3 CLO BUZ
I I/O I/O I/O
19 29-32 23 24
P1.2 P6.0-P6.3 P2.2 P2.3
Input Input Input Input
A-4 D D D
XIN, XOUT
-
12,11
-
-
-
XTIN, XTOUT
-
14,15
-
-
-
VDD VSS
RESET
- - - -
9 10 16 13
- - - -
- - Input -
- - B -
TEST
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
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KS57C2302/C2304/P2304 MICROCONTROLLER
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-CHANNEL IN N-CHNNEL
DATA
P-CHANNEL OUT N-CHANNEL
OUTPUT DISABLE
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type C
VDD VDD PULL-UP RESISTOR P-CHANNEL RESISTOR ENABLE PULL-UP RESISTOR RESISTOR ENABLE DATA IN OUTPUT DISABLE CIRCUIT TYPE C P-CHANNEL
I/O
SCHMITT TRIGGER
CIRCUIT TYPE A
Figure 1-4. Pin Circuit Type A-4 (P1)
Figure 1-6. Pin Circuit Type D (P2, P3, and P6)
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PRODUCT OVERVIEW
KS57C2302/C2304/P2304 MICROCONTROLLER
VLC0 VDD
VLC1
LCD SEGMENT/ COMMON DATA
OUT
IN
SCHMITT TRIGGER VLC2
Figure 1-9. Pin Circuit Type B (RESET) Figure 1-7. Pin Circuit Type H (SEG/COM)
VDD VLC0
VLC1
LCD SEGMENT/ & PORT 8 DATA
OUT
VLC2
Figure 1-8. Pin Circuit Type H-1 (P8)
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
PROGRAM MEMORY (ROM)
ROM maps for KS57C2302/C2304 devices are mask programmable at the factory. KS57C2302 has 2K x 8-bit program memory and KS57C2304 has 4K x 8-bit program memory, aside from the differences in the ROM size the two products are identical in other features. In its standard configuration, the device's 4,096 x 8-bit program memory has four areas that are directly addressable by the program counter (PC): -- 12-byte area for vector addresses -- 96-byte instruction reference area -- 20-byte general-purpose area -- 1920-byte general-purpose area (KS57C2302) 3968-byte general-purpose area (KS57C2304) General-Purpose Program Memory Two program memory areas are allocated for general-purpose use: One area is 20 bytes in size and the other is 1,920 bytes (KS57C2302) or 3,968 bytes (KS57C2304). Vector Addresses A 12-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corresponding service routines. The 12-byte area can be used alternately as general-purpose ROM. REF Instructions Locations 0020H-007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte instructions, and 3-byte instructions which are stored in the look-up table. Unused look-up table addresses can be used as general-purpose ROM. Table 2-1. Program Memory Address Ranges ROM Area Function Vector address area General-purpose program memory REF instruction look-up table area General-purpose program memory Address Ranges 0000H-000BH 000CH-001FH 0020H-007FH 0080H-7FFH (KS57C2302) 0080H-0FFFH (KS57C2304) Area Size (in Bytes) 12 20 96 1920 (KS57C2302) 3968 (KS57C2304)
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
GENERAL-PURPOSE MEMORY AREAS The 20-byte area at ROM locations 000CH-001FH and the 3,968-byte area at ROM locations 0080H-0FFFH are used as general-purpose program memory. Unused locations in the vector address area and REF instruction look-up table areas can be used as general-purpose program memory. However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the ROM. VECTOR ADDRESS AREA The 12-byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines. 12-byte vector addresses are organized as follows: EMB PC7 ERB PC6 0 PC5 0 PC4 PC11 PC3 PC10 PC2 PC9 PC1 PC8 PC0
To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the next page explain how to do this.
0000H VECTOR ADDRESS AREA (12 Bytes)
000BH 000CH 001FH 0020H
7 0000H
6
5
4
3
2
1
0
GENERAL-PURPOSE AREA (20 Bytes)
RESET
0002H
INSTRUCTION REFERENCE AREA
INTB
0004H
INT0
007FH 0080H
0006H
INT1
GENERAL-PURPOSE AREA (1,920 Bytes 3,968 Bytes)
0008H
Reserved
000AH
INTT0
7FFH 0FFFH
Figure 2-1. ROM Address Structure
Figure 2-2. Vector Address Structure
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
+ PROGRAMMING TIP -- Defining Vectored Interrupts
The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: ORG VENT0 VENT1 VENT2 VENT3 ORG VENT5 0000H 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 000AH 0,0,INTT0 ; EMB 0, ERB 0; Jump to INTT0 address ; ; ; ; EMB EMB EMB EMB 1, ERB 0, ERB 0, ERB 0, ERB 0; Jump to RESET address 0; Jump to INTB address 0; Jump to INT0 address 0; Jump to INT1 address
2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations: ORG VENT0 VENT1 ORG VENT3 ORG 0000H 1,0,RESET 0,0,INTB 0006H 0,0,INT1 0010H ; ; ; ; EMB 1, ERB 0; Jump to RESET address EMB 0, ERB 0; Jump to INTB address INT0 interrupt not used EMB 0, ERB 0; Jump to INT1 address
3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a ORG instruction as in Example 2, a CPU malfunction will occur: ORG VENT0 VENT1 VENT3 VENT5 ORG 0000H 1,0,RESET 0,0,INTB 0,0,INT1 0,0,INTT0 0010H ; ; ; ; EMB EMB EMB EMB 1, ERB 0, ERB 0, ERB 0, ERB 0; Jump to RESET address 0; Jump to INTB address 0; Jump to INT0 address 0; Jump to INT1 address
General-purpose ROM area In this example, when an INT1 interrupt is generated, the corresponding vector area is not VENT3 INT1, but VENT5 INTT0. This causes an INT1 interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur.
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020H-007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations in the REF look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. By using REF instructions to execute instructions larger than one byte, you can improve program execution time considerably by reducing the number of program steps. In summary, there are three ways you can use the REF instruction: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions, -- Branching to any location by referencing a branch instruction stored in the look-up table, -- Calling subroutines at any location by referencing a call instruction stored in the look-up table.
+ PROGRAMMING TIP -- Using the REF Look-Up Table
Here is one example of how to use the REF instruction look-up table: JMAIN KEYCK WATCH INCHL ORG TJP BTSF TCALL LD INCS * * * LD ORG NOP NOP * * * REF REF REF REF REF * * * 0020H MAIN KEYFG CLOCK @HL,A HL ; ; ; ; 0, MAIN 1, KEYFG CHECK 2, CALL CLOCK 3, (HL) A
ABC MAIN
EA,#00H 0080H
; 47, EA #00H
KEYCK JMAIN WATCH INCHL ABC
; ; ; ; ; ;
BTSF KEYFG (1-byte instruction) KEYFG = 1, jump to MAIN (1-byte instruction) KEYFG = 0, CALL CLOCK (1-byte instruction) LD @HL,A INCS HL LD EA,#00H (1-byte instruction)
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
DATA MEMORY (RAM)
OVERVIEW In its standard configuration, the 288 x 4-bit data memory has three areas: -- 32 x 4-bit working register area in bank 0 -- 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area -- 32 x 4-bit area for LCD data in bank 1 -- 128 x 4-bit area in bank 15 for memory-mapped I/O addresses To make it easier to reference, the data memory area has three memory banks -- bank 0, bank 1, and bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. One exception is the LCD data register area, which is 1-bit and 4-bit addressable only. Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset. However, when RESET signal is generated in power-down mode, the data memory contents are held.
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
000H WORKING REGISTERS (32 x 4 Bits) 01FH 020H GENERAL-PURPOSE REGISTERS AND STACK AREA (224 x 4 Bits) BANK 0
0FFH
~
1E0H 1FFH LCD DATA REGISTERS (32 x 4 Bits)
~
BANK 1
~
F80H MEMORY-MAPPED I/O AEERESS REGISTERS (128 x 4 Bits) FFFH
~
BANK 15
Figure 2-3. Data Memory (RAM) Map
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
Memory Banks 0, 1, and 15 Bank 0 (000H-0FFH) The lowest 32 nibbles of bank 0 (000H-01FH) are used as working registers; the next 224 nibbles (020H-0FFH) can be used both as stack area and as general-purpose data memory. Use the stack area for implementing subroutine calls and returns, and for interrupt processing. 32 nibbles of bank 1 are used as display registers or general purpose memory. The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed RAM locations for each peripheral hardware address are mapped into this area.
Bank 1 Bank 15
(1E0H-1FFH) (F80H-FFFH)
Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. With direct addressing, you can access locations 000H-07FH of bank 0 and bank 15. With indirect addressing, only bank 0 (000H-0FFH) can be accessed. When the EMB flag is set to logic one, all three data memory banks can be accessed according to the current SMB value. For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to address RAM locations, remember to use the even-numbered register address as the instruction operand. Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 1. Register locations in this area that are not used to store LCD data can be assigned to general-purpose use.
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 2-2. Data Memory Organization and Addressing Addresses 000H-01FH 020H-0FFH 1E0H-1FFH F80H-FFFH Register Areas Working registers Stack and general-purpose registers LCD Data registers I/O-mapped hardware registers 1 15 1 0, 1 1 15 Bank 0 EMB Value 0, 1 SMB Value 0
+ PROGRAMMING TIP -- Clearing Data Memory Banks 0 and 1
Clear banks 0 and 1 of the data memory area: RAMCLR BITS SMB LD LD LD INCS JR SMB LD LD INCS JR EMB 1 HL, #0E0H A, #0H @HL, A HL RMCL1 0 HL, #10H @HL, A HL RMCL0 ; RAM (1E0H-1FFH) clear
RMCL1
; RAM (010H-0FFH) clear
RMCL0
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
WORKING REGISTERS Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units.
000H 001H
A
E
002H L 003H H 004H X 005H DATA 006H MEMORY BANK 0 007H 008H A 00FH 010H 017H 018H 01FH A W Z Y WORKING REGISTER BANK 0
... Y ... Y ... Y
REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3
A
Figure 2-4. Working Register Map
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
Working Register Banks For addressing purposes, the working register area is divided into four register banks -- bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRB n) and by setting the status of the register bank enable flag (ERB). Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. Table 2-3. Working Register Organization and Addressing ERB Setting 0 1 SRB Settings 3 0 0 2 0 0 1 - 0 0 1 1 Paired Working Registers Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E, and A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ, and WL. Registers A, L, X, and Z always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. 0 - 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3 Selected Register Bank
(MSB) Y
(LSB)
(MSB) Z
(LSB)
W
X
H
L
E
A
Figure 2-5. Register Pair Configuration
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
Special-Purpose Working Registers Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also be used as a 1-bit accumulator. 8-bit double registers WX, WL, and HL are used as data pointers for indirect addressing. When the HL register serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction.
C
1-BIT ACCUMULATOR 4-BIT ACCUMULATOR 8-BIT ACCUMULATOR
A
EA
Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction.
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Selecting the Working Register Area
The following examples show the correct programming method for selecting working register area: 1. When ERB = "0": VENT2 INT0 1,0,INT0 PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET SB 2 HL WX YZ EA 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA EA YZ WX HL SB ; EMB 1, ERB 0, Jump to INT0 address ; ; ; ; ; ; PUSH current SMB, SRB Instruction does not execute because ERB = "0" PUSH HL register contents to stack PUSH WX register contents to stack PUSH YZ register contents to stack PUSH EA register contents to stack
; ; ; ; ;
POP EA register contents from stack POP YZ register contents from stack POP WX register contents from stack POP HL register contents from stack POP current SMB, SRB
The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values, as shown in Example 2 below. 2. When ERB = "1": VENT2 INT0 1,1,INT0 PUSH SRB SMB LD LD LD INCS LD LD POP IRET SB 2 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA SB ; EMB 1, ERB 1, Jump to INT0 address ; Store current SMB, SRB ; Select register bank 2 because of ERB = "1"
; Restore SMB, SRB
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
STACK OPERATIONS
STACK POINTER (SP) The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always remain cleared to logic zero. F80H F81H SP3 SP7 SP2 SP6 SP1 SP5 "0" SP4
There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack. The program counter contents and program status word (PSW) are stored in the stack area prior to the execution of a CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) type. The stack area is located in general-purpose data memory bank 0. During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed. The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00H. This sets the first register of the stack area to 0FFH. NOTE A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. To do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly.
+ PROGRAMMING TIP -- Initializing the Stack Pointer
To initialize the stack pointer (SP): 1. When EMB = "1": SMB LD LD 2. When EMB = "0": LD LD EA,#00H SP,EA ; Memory addressing area (00H-7FH, F80H-FFFH) 15 EA,#00H SP,EA ; Select memory bank 15 ; Bit 0 of SP is always cleared to "0" ; Stack area initial address (0FFH) (SP) - 1
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decreased by a number determined by the type of push operation and then points to the next available stack location. PUSH Instructions A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH has executed, the SP is decreased by two and points to the next available stack location. CALL Instructions When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to the number of levels permitted in the stack. Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is decreased by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area.
INTERRUPT PUSH
(After PUSH, SP SP - 2)
CALL
(After CALL, SP SP - 6 SP - 5 SP - 4 SP - 3 0 SP - 6) SP - 6 0 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP
(When INT is acknowledged, SP SP - 6) PC11- PC8 0 0 0 0
PC11- PC8 0 0
PC3 - PC0 PC7 - PC4 0 0 0 EMB ERB PSW 0 0 0
PC3 - PC0 PC7 - PC4 IS1 C IS0 EMB ERB PSW SC2 SC1 SC0
SP - 2 SP - 1 SP
LOWER REGISTER UPPER REGISTER
SP - 2 SP - 1 SP
Figure 2-7. Push-Type Stack Operations
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by the type of operation and points to the next free stack location. POP Instructions A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. After the POP has executed, the SP is incremented by two and points to the next free stack location. RET and SRET Instructions The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location. IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has executed, the SP is incremented by six and points to the next free stack location.
POP
(SP SP SP + 1 SP + 2 SP + 2) SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0
RET OR SRET
(SP SP + 6) SP 0 SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 IS1 C 0 (SP
IRET
SP + 6)
LOWER UPPER
PC11 - PC8 0 0
PC11 - PC8 0 0 0
PC3 - PC0 PC7 - PC4 0 EMB ERB PSW 0 0 0
PC3 - PC0 PC7 - PC4 IS0 EMB ERB PSW SC2 SC1 SC0
Figure 2-8. Pop-Type Stack Operations
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
BIT SEQUENTIAL CARRIER (BSC)
The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero. Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the L register. BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately. If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3. Table 2-4. BSC Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H Bit 3 BSC0.3 BSC1.3 BSC2.3 BSC3.3 Bit 2 BSC0.2 BSC1.2 BSC2.2 BSC3.2 Bit 1 BSC0.1 BSC1.1 BSC2.1 BSC3.1 Bit 0 BSC0.0 BSC1.0 BSC2.0 BSC3.0
+ PROGRAMMING TIP -- Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin: BITS SMB LD LD LD LD SMB LD LDB LDB INCS JR RET EMB 15 EA,#37H BSC0,EA EA,#59H BSC2,EA 0 L,#0H C,BSC0.@L P3.0,C L AGN
; ; BSC0 A, BSC1 E ; ; BSC2 A, BSC3 E ; ; ; P3.0 C
AGN
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ADDRESS SPACES
PROGRAM COUNTER (PC)
A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1byte REF instruction which is used to reference instructions stored in the ROM.
PROGRAM STATUS WORD (PSW)
The program status word (PSW) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW values are mapped as follows: (MSB) FB0H FB1H IS1 C IS0 SC2 EMB SC1 (LSB) ERB SC0
The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag. Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address. When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logical zero. Table 2-5. Program Status Word Bit Descriptions PSW Bit Identifier IS1, IS0 EMB ERB C SC2, SC1, SC0 Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Bit Addressing 1, 4 1 1 1 8 Read/Write R/W R/W R/W R/W R
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the IPR. When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings. Table 2-6. Interrupt Status Flag Bit Settings IS1 Value 0 0 1 1 IS0 Value 0 1 0 1 Status of Currently Executing Process 0 1 2 - Effect of IS0 and IS1 Settings on Interrupt Request Control All interrupt requests are serviced Only high-priority interrupt(s) as determined in the interrupt priority register (IPR) are serviced No more interrupt requests are serviced Not applicable; these bit settings are undefined
Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to re-enable interrupt processing.
+ PROGRAMMING TIP -- Setting ISx Flags for Interrupt Processing
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing: INTB BITR BITS EI DI IS1 IS0 ; ; ; ; Disable interrupt IS1 0 Allow interrupts according to IPR priority level Enable interrupt
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ADDRESS SPACES
EMB FLAG (EMB) The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1, or 15. When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H-07FH of memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the general-purpose areas of bank 0, 1, and 15 can be accessed by using the appropriate SMB value.
+ PROGRAMMING TIP -- Using the EMB Flag to Select Memory Banks
EMB flag settings for memory bank selection: 1. When EMB = "0": SMB LD LD LD SMB LD LD SMB LD LD 2. When EMB = "1": SMB LD LD LD SMB LD LD SMB LD LD 1 A,#9H 0E0H,A 0F0H,A 0 90H,A 34H,A 15 20H,A 90H,A ; Select memory bank 1 ; ; ; ; ; ; ; ; (1E0H) A, bank 1 is selected (1F0H) A, bank 1 is selected Select memory bank 0 (090H) A, bank 0 is selected (034H) A, bank 0 is selected Select memory bank 15 Program error, but assembler does not detect it (F90H) A, bank 15 is selected 1 A,#9H 90H,A 34H,A 0 90H,A 34H,A 15 20H,A 90H,A ; Non-essential instruction since EMB = "0" ; ; ; ; ; ; ; ; (F90H) A, bank 15 is selected (034H) A, bank 0 is selected Non-essential instruction since EMB = "0" (F90H) A, bank 15 is selected (034H) A, bank 0 is selected Non-essential instruction, since EMB = "0" (020H) A, bank 0 is selected (F90H) A, bank 15 is selected
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (SRB). When an internal reset is generated, bit 6 of program memory address 0000H is written to the ERB flag. This automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is executed. During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions.
+ PROGRAMMING TIP -- Using the ERB Flag to Select Register Banks
ERB flag settings for register bank selection: 1. When ERB = "0": SRB LD LD SRB LD SRB LD 2. When ERB = "1": SRB LD LD SRB LD SRB LD 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; Register bank 1 is selected Bank 1 EA #34H Bank 1 HL Bank 1 EA Register bank 2 is selected Bank 2 YZ BANK2 EA Register bank 3 is selected Bank 3 WX Bank 3 EA 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; ; Register bank 0 is selected (since ERB = "0", the SRB is configured to bank 0) Bank 0 EA #34H Bank 0 HL EA Register bank 0 is selected Bank 0 YZ EA Register bank 0 is selected Bank 0 WX EA
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESS SPACES
SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed. CARRY FLAG (C) The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations involving bit-addressed data memory. If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation SCF RCF CCF BTST C Bit transfer LDB (operand)
(1) ,C
Instructions
Carry Flag Manipulation Set carry flag to "1" Clear carry flag to "0" (reset carry flag) Invert carry flag value (complement carry flag) Test carry and skip if C = "1" Load carry flag value to the specified bit Load contents of the specified bit to carry flag AND the specified bit with contents of carry flag and save the result to the carry flag OR the specified bit with contents of carry flag and save the result to the carry flag XOR the specified bit with contents of carry flag and save the result to the carry flag Save carry flag to stack with other PSW bits Restore carry flag from stack with other PSW bits
LDB C,(operand) (1) Boolean manipulation BAND C,(operand) (1) BOR C,(operand) (1) BXOR C,(operand) (1) Interrupt routine Return from interrupt INTn (2) IRET
NOTES: 1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b. 2. 'INTn' refers to the specific interrupt being executed and is not an instruction.
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ADDRESS SPACES
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Using the Carry Flag as a 1-Bit Accumulator
1. Set the carry flag to logic one: SCF LD LD ADC ; ; ; ; C1 EA #0C3H HL #0AAH EA #0C3H + #0AAH + #1H, C 1
EA,#0C3H HL,#0AAH EA,HL
2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P2.0: LD LDB BAND LDB H,#3H C,@H+0FH.3 C,P3.3 P2.0,C ; ; ; ; ; Set the upper four bits of the address to the H register value C bit 3 of 3FH C C AND P3.3 Output result from carry flag to P2.0
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESSING MODES
3
OVERVIEW
ADDRESSING MODES
The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the addressable area in the RAM is restricted to specific locations. The EMB flag works in connection with the select memory bank instruction, SMB n. You will recall that the SMB n instruction is used to select RAM bank 0, 1, or 15. The SMB setting is always contained in the upper four bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1, or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations are addressable at all times, regardless of the current EMB flag setting. Here are a few guidelines to keep in mind regarding data memory addressing: -- When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. -- Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing. -- With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
3-1
ADDRESSING MODES
KS57C2302/C2304/P2304 MICROCONTROLLER
RAM AREAS 000H 01FH 020H 07FH 080H
ADDRESSING MODE
DA DA.b EMB = 0 EMB = 1
@HL @H + DA.b EMB = 0 EMB = 1
@WX @WL X
mema.b X
memb.@L X
WORKING REGISTERS
SMB = 0 BANK 0 (GENERAL REGISTERS AND STACK)
SMB = 0
0FFH
~ ~
~ ~
1E0H
BANK 1 (DISPLAY REGISTERS)
SMB = 1
SMB = 1
1FFH F80H BANK 15 (PERIPHERAL HARDWARE REGISTERS) FFFH FB0H FBFH FC0H
SMB = 15
SMB = 15
FF0H NOTES 1. 'X' means don't care. 2. Blank columns indicate RAM areas that are not addressable, given the addressing method and enable memory bank (EMB) flag setting shown in the column headers.
Figure 3-1. RAM Address Structure
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESSING MODES
EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine has completed. At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR) despite the current SMB setting.
+ PROGRAMMING TIP -- Initializing the EMB and ERB Flags
The following assembly instructions show how to initialize the EMB and ERB flag settings: ORG VENT0 VENT1 VENT2 VENT3 ORG VENT5 * * * BITR 0000H 1,0,RESET 0,1,INTB 0,1,INT0 0,1,INT1 000AH 0,1,INTT0 ; ; ; ; ; ; ; ROM address assignment EMB 1, ERB 0, branch RESET EMB 0, ERB 1, branch INTB EMB 0, ERB 1, branch INT0 EMB 0, ERB 1, branch INT1 ROM address assignment EMB 0, ERB 1, branch INTT0
RESET
EMB
3-3
ADDRESSING MODES
KS57C2302/C2304/P2304 MICROCONTROLLER
ENABLE MEMORY BANK SETTINGS EMB = "1" When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0, 1, or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows: If SMB = 0, If SMB = 1, If SMB = 15, EMB = "0" When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. If EMB = "0", the addressable area is restricted to locations 000H-07FH in bank 0 and to locations F80H-FFFH in bank 15 for direct addressing. For indirect addressing, only locations 000H-0FFH in bank 0 are addressable, regardless of SMB value. To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to "1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM address 0000H. EMB-Independent Addressing At any time, several areas of the data memory can be addressed independent of the current status of the EMB flag. These exceptions are described in Table 3-1. 000H-0FFH 1E0H-1FFH F80H-FFFH
Table 3-1. RAM Addressing Not Affected by the EMB Value Address 000H-0FFH Addressing Method 4-bit indirect addressing using WX and WL register pairs; 8-bit indirect addressing using SP 1-bit direct addressing 1-bit indirect addressing using the L register Affected Hardware Not applicable LD PUSH POP PSW, SCMOD, IEx, IRQx, I/O BSC, I/O BITS BITR Program Examples A,@WX EA EA EMB IE4
FB0H-FBFH FF0H-FFFH FC0H-FFFH
BTST FC3H.@L BAND C,P3.@L
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KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESSING MODES
SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3-2. During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB instruction. You later restore the value to the SB using the POP SB instruction.
SMB (F83H) SB REGISTER SMB 3 SMB 2 SMB 1 SMB 0 0
SRB (F82H) 0 SRB 1 SRB 0
Figure 3-2. SMB and SRB Values in the SB Register Select Register Bank (SRB) Instruction The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, and 3. One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls. RESET clears the 4-bit SRB value to logic zero. Select Memory Bank (SMB) Instruction To select one of the four available data memory banks, you must execute an SMB n instruction specifying the number of the memory bank you want (0, 1, or 15). For example, the instruction 'SMB 1' selects bank 1 and 'SMB 15' selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB flag setting.) The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB value to logic zero. The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls.
3-5
ADDRESSING MODES
KS57C2302/C2304/P2304 MICROCONTROLLER
DIRECT AND INDIRECT ADDRESSING 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. Indirect addressing specifies a memory location that contains the required direct address. The KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM address must always be used as the instruction operand.
1-BIT ADDRESSING Table 3-2. 1-Bit Direct and Indirect RAM Addressing Operand Notation DA.b Addressing Mode Description Direct: bit is indicated by the RAM address (DA), memory bank selection, and specified bit number (b). mema.b Direct: bit is indicated by addressable area (mema) and bit number (b). Indirect: lower two bits of register L as indicated by the upper 6 bits of RAM area (memb) and the upper two bits of register L. Indirect: bit indicated by the lower four bits of the address (DA), memory bank selection, and the H register identifier.
NOTE: x = not applicable.
EMB Flag Setting 0 1
Addressable Area 000H-07FH F80H-FFFH 000H-0FFH 1E0H-1FFH F80H-FFFH
Memory Bank Bank 0 Bank 15 Bank 0 Bank 1 Bank 15 Bank 15
Hardware I/O Mapping - All 1-bit addressable peripherals (SMB = 15) IS0, IS1, EMB, ERB, IEx, IRQx, Pn.n BSCn.x Pn.n
x
FB0H-FBFH FF0H-FFFH FC0H-FFFH
memb.@L
x
Bank 15
@H + DA.b
0 1
000H-0FFH 000H-0FFH 1E0H-1FFH F80H-FFFH
Bank 0 Bank 0 Bank 1 Bank 15 All 1-bit
- addressable peripherals (SMB = 15)
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ADDRESSING MODES
+ PROGRAMMING TIP -- 1-Bit Addressing Modes
1-Bit Direct Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P3.0
; ; ; ; ;
34H.3 1 F85H.3 1 If FBAH.0 = 1, skip Else if, FBAH.0 = 0, F85H.3 (BMOD.3) 1 FF3H.0 (P3.0) 1
2. If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P3.0
; ; ; ; ;
34H.3 1 85H.3 1 If 0BAH.0 = 1, skip Else if 0BAH.0 = 0, 085H.3 1 FF3H.0 (P3.0) 1
1-Bit Indirect Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG
; H #0BH ; If 0BAH.0 = 1, 0BAH.0 0 and skip ; Else if 0BAH.0 = 0, FBAH.0 1
2.If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG
; H #0BH ; If 0BAH.0 = 1, 0BAH.0 0 and skip ; Else if 0BAH.0 = 0, 0BAH.0 1
3-7
ADDRESSING MODES
KS57C2302/C2304/P2304 MICROCONTROLLER
4-BIT ADDRESSING Table 3-3. 4-Bit Direct and Indirect RAM Addressing Operand Notation DA Direct: 4-bit address indicated by the RAM address (DA) and the memory bank selection @HL Indirect: 4-bit address indicated by the memory bank selection and register HL 0 1 1 Addressing Mode Description EMB Flag Setting 0 Addressable Area 000H-07FH F80H-FFFH 000H-0FFH 1E0H-1FFH F80H-FFFH 000H-0FFH 000H-0FFH 1E0H-1FFH F80H-FFFH @WX @WL Indirect: 4-bit address indicated by register WX Indirect: 4-bit address indicated by register WL x x 000H-0FFH 000H-0FFH Memory Bank Bank 0 Bank 15 Bank 0 Bank 1 Bank 15 Bank 0 Bank 0 Bank 1 Bank 15 Bank 0 Bank 0 Hardware I/O Mapping - All 4-bit addressable peripherals (SMB = 15) - All 4-bit addressable peripherals (SMB = 15) -
NOTE: x = not applicable.
3-8
KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESSING MODES
+ PROGRAMMING TIP -- 4-Bit Addressing Modes
4-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A
; ; ; ; ;
Non-essential instruction, since EMB = "0" A (P3) Non-essential instruction, since EMB = "0" (046H) A (F8EH (LCON)) A
2. If EMB = "1": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A
; A (P3) ; (046H) A ; (08EH) A
4-Bit Indirect Addressing 1. If EMB = "0", compare bank 0 locations 040H-046H with bank 0 locations 060H-066H: ADATA BDATA EQU EQU SMB LD LD LD CPSE SRET DECS JR RET 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL L COMP
; Non-essential instruction, since EMB = "0" ; A bank 0 (040H-046H) ; If bank 0 (060H-066H) = A, skip
COMP
2. If EMB = "0", exchange bank 0 locations 040H-046H with bank 0 locations 060H-066H: ADATA BDATA EQU EQU SMB LD LD LD XCHD JR 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
; Non-essential instruction, since EMB = "0" ; A bank 0 (040H-046H) ; Bank 0 (060H-066H) A
TRANS
3-9
ADDRESSING MODES
KS57C2302/C2304/P2304 MICROCONTROLLER
8-BIT ADDRESSING Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instruction Notation DA Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection @HL Indirect: the 8-bit address 4-bit indicated by the memory bank selection and register HL; (the L register value must be an even number) 0 1 1 Addressing Mode Description EMB Flag Setting 0 Addressable Area 000H-07FH F80H-FFFH 000H-0FFH 1E0H-1FFH F80H-FFFH 000H-0FFH 000H-0FFH 1E0H-1FFH F80H-FFFH Memory Bank Bank 0 Bank 15 Bank 0 Bank 1 Bank 15 Bank 0 Bank 0 Bank 1 Bank 15 Hardware I/O Mapping - All 8-bit addressable peripherals (SMB = 15) - All 8-bit addressable peripherals (SMB = 15)
3-10
KS57C2302/C2304/P2304 MICROCONTROLLER
ADDRESSING MODES
+ PROGRAMMING TIP -- 8-Bit Addressing Modes
8-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU LD SMB LD LD 46H 8EH EA, #0FFH 0 ADATA,EA BDATA,EA
; (046H) A, (047H) E ; (F8EH) A, (F8FH) E
2. If EMB = "1": ADATA BDATA EQU EQU SMB LD LD LD 46H 8EH 0 EA, #0FFH ADATA,EA BDATA,EA
; (046H) A, (047H) E ; (08EH) A, (08FH) E
8-Bit Indirect Addressing 1. If EMB = "0": ADATA EQU SMB LD LD 46H 1 HL,#ADATA EA,@HL ; Non-essential instruction, since EMB = "0" ; A (046H), E (047H)
3-11
ADDRESSING MODES
KS57C2302/C2304/P2304 MICROCONTROLLER
NOTES
3-12
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
4
OVERVIEW
MEMORY MAP
To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current EMB value. I/O MAP FOR HARDWARE REGISTERS Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations F80H-FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map gives you the following information: -- Register address -- Register name (mnemonic for program addressing) -- Bit values (both addressable and non-manipulable) -- Read-only, write-only, or read and write addressability -- 1-bit, 4-bit, or 8-bit data manipulation characteristics
4-1
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 4-1. I/O Map for Memory Bank 15 Memory Bank 15 Address F80H F81H F85H F86H F87H F88H F89H F8CH F8DH F8EH F90H F91H F92H F94H F95H F96H F97H F98H F99H F9AH FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H IPR PCON IMOD0 IMOD1 IMOD2 SCMOD WDFLAG PSW WDMOD TREF0 TCNT0 LCON TMOD0 LMOD WMOD BMOD BCNT Register SP Bit 3 .3 .7 .3 .3 .7 .3 .7 .3 .7 "0"
(4)
Addressing Mode Bit 1 .1 .5 .1 .1 .5 .1 .5 .1 .5 "0" "0" .5 "u" (4) .1 .5 .1 .5 .1 .5 "0" EMB SC1 .1 .1 .1 "0" .1 "0" Bit 0 "0" .4 .0 .0 .4 .0 .4 .0 .4 .0 "0" .4 "u" (4) .0 .4 .0 .4 .0 .4 "0" ERB SC0 .0 .0 .0 .0 .0 .0 W Yes No No W R/W R W W W Yes Yes No IME No No Yes Yes No Yes Yes Yes No No No No Yes W No No Yes W No No Yes R/W R Yes No No No No Yes W W No .3 Yes No No Yes W .3 No Yes W .3 (1) No Yes W R .3 No Yes No No Yes R/W R/W 1-Bit No 4-Bit No 8-Bit Yes
Bit 2 .2 .6 .2 .2 .6 .2 "0" .2 .6 .2 .2 .6 TOE0 .2 .6 .2 .6 .2 .6 "0" IS0 SC2 .2 .2 "0" "0" "0" .2
Locations F82H-F84H are not mapped.
Locations F8AH-F8BH are not mapped.
Location F8FH is not mapped. .3 "0" "u" (4) .3 .7 .3 .7 .3 .7 .3 IS1 C (2) IME .3 .3 "0" "0" .3
Location F93H is not mapped.
Locations F9BH-FAFH are not mapped.
4-2
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
Table 4-1. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FB8H FBAH FBCH FBEH FBFH FC0H FC1H FC2H FC3H FD0H FDCH FDDH FE8H FE9H FECH FEDH FF1H FF2H FF3H FF6H Port 1 Port 2 Port 3 Port 6 PMG2 PMG1 Register INT (A) INT (B) INT (C) INT (E) INT (F) BSC0 BSC1 BSC2 BSC3 CLMOD PUMOD Bit 3 "0" "0" "0" IE1 "0" .3 .3 .3 .3 .3 PM.3 "0" PM3.3 PM6.3 "0" "0" .3 .3 .3 .3 Bit 2 "0" "0" "0" IRQ1 "0" .2 .2 .2 .2 "0" PM.2 PM.6 PM3.2 PM6.2 PM2 "0" .2 .2 .2 .2 Bit 1 IEB IEW IET0 IE0 IE2 .1 .1 .1 .1 .1 PM.1 "0" PM3.1 PM6.1 "0" "0" .1 .1 .1 .1 Bit 0 IRQB IRQW IRQT0 IRQ0 IRQ2 .0 .0 .0 .0 .0 "0" "0" PM3.0 PM6.0 "0" "0" .0 .0 .0 .0 R R/W R/W R/W Yes Yes Yes Yes Yes Yes Yes Yes No No No No W No No Yes W No No Yes W W No No Yes No No Yes R/W Yes Yes Yes R/W R/W R/W R/W R/W Addressing Mode 1-Bit Yes Yes Yes Yes 4-Bit Yes Yes Yes Yes 8-Bit No No No No
Location FB9H is not mapped Location FBBH is not mapped. Location FBDH is not mapped.
Locations FD1H-FDBH are not mapped.
Locations FDEH-FE7H are not mapped.
Locations FEAH-FEBH are not mapped.
Locations FEEH-FF0H are not mapped.
Locations FF4H-FF5H are not mapped. Locations FF7H-FFFH are not mapped.
NOTES: 1. Bit 3 in the WMOD register is read only. 2. The carry flag can be read or written by specific bit manipulation instructions only. 3. The LCON.3 register must be set to "0". 4. "u" means that the value is undetermined.
4-3
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
REGISTER DESCRIPTIONS In this section, register descriptions are presented in a consistent format to familiarize you with the memorymapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description format. Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference source when writing application programs. Counter registers and reference registers, as well as the stack pointer and port I/O latches, are not included in these descriptions. More detailed information about how these registers are used is included in Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module descriptions.
4-4
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
Register and bit IDs used for bit addressing Register ID Register name
Name of individual bit or related bits Associated hardware module Register location in RAM bank 15
CLMOD- Clock Output Mode Control Register Bit Identifier
RESET
CPU 1 .1 0 W 4 0 .0 0 W 4
FD0H
3 .3 Value 0 W 4
2 .2 0 W 4
Read/Write Bit Addressing CLMOD.3
Enable/Disable Clock Output Control Bit 0 1 Disable clock output Enable clock output
CLMOD.2
Bit 2 0 Always logic zero
CLMOD.1 - .0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source Select system clock fxx/8 (524 kHz at 4.19 MHz) Select system clock fxx/16 (262 kHz at 4.19 MHz) Select system clock fxx/64 (65.5 kHz at 4.19 MHz)
R = Read-only W = Write-only R/W =Read/write
Bit value immediately following a RESET
Bit number in MSB to LSB order
Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit)
Description of the effect of specific bit settings
Bit identifier used for bit addressing
Figure 4-1. Register Description Format
4-5
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
BMOD -- Basic Timer Mode Register
Bit Identifier
RESET
F85H
1 .1 0 W 4 0 .0 0 W 4
3 .3 0 W 1/4 Value
2 .2 0 W 4
Read/Write Bit Addressing .3
Basic Timer Restart Bit 1 Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero
.2-.0
Input Clock Frequency and Signal Stabilization Interval Control Bits 0 0 1 1 0 1 0 1 0 1 1 1 Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: fxx / 212 (1.02 kHz) 220 / fxx (250 ms) fxx / 29 (8.18 kHz) 217 / fxx (31.3 ms) fxx / 27 (32.7 kHz) 215 / fxx (7.82 ms) fxx / 25 (131 kHz) 213 / fxx (1.95 ms)
NOTES: 1. Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. The stabilization interval can also be interpreted as "Interrupt Interval Time". 2. When a RESET occurs, the oscillation stabilization time is 31.3 ms (217/fxx) at 4.19 MHz. 3. 'fxx' is the system clock rate given a clock frequency of 4.19 MHz.
4-6
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
CLMOD -- Clock Output Mode Register
Bit Identifier
RESET
FD0H
0 .0 0 W 4
3 .3 0 W 4 Value
2 "0" 0 W 4
1 .1 0 W 4
Read/Write Bit Addressing .3
Enable/Disable Clock Output Control Bit 0 1 Disable clock output Enable clock output
.2
Bit 2 0 Always logic zero
.1-.0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source fx/4, fx/8, fx/64 or fxt/4 (1.05 MHz, 524 kHz, 65.5 kHz or 8.192KHz) Select system clock fxx/8 (524 kHz) Select system clock fxx/16 (262 kHz) Select system clock fxx/64 (65.5 kHz)
NOTE: 'fxx' and 'fx' is the system clock and the main clock respectively, given a clock frequency of 4.19 MHz. 'fxt' is the sub clock, given a clock frequency of 32.768KHz.
4-7
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
IE0, 1, IRQ0, 1 -- INT0, 1 Interrupt Enable/Request Flags
Bit Identifier
RESET
FBEH
3 IE1 0 R/W 1/4 Value
2 IRQ1 0 R/W 1/4
1 IE0 0 R/W 1/4
0 IRQ0 0 R/W 1/4
Read/Write Bit Addressing IE1
INT1 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT1 pin Enable interrupt requests at the INT1 pin
IRQ1
INT1 Interrupt Request Flag - Generate INT1 interrupt (This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin.)
IE0
INT0 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT0 pin Enable interrupt requests at the INT0 pin
IRQ0
INT0 Interrupt Request Flag - Generate INT0 interrupt (This bit is set and cleared automatically by hardware when rising or falling edge detected at INT0 pin.)
4-8
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
IE2, IRQ2 -- INT2 Interrupt Enable/Request Flags
Bit Identifier
RESET
FBFH
3 "0" 0 R/W 1/4 Bits 3-2 0 Value
2 "0" 0 R/W 1/4
1 IE2 0 R/W 1/4
0 IRQ2 0 R/W 1/4
Read/Write Bit Addressing .3-.2
Always logic zero
IE2
INT2 Interrupt Enable Flag 0 1 Disable INT2 interrupt requests at the INT2 pin Enable INT2 interrupt requests at the INT2 pin
IRQ2
INT2 Interrupt Request Flag - Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2. Since INT2 is a quasi-interrupt, IRQ2 flag must be cleared by software.)
4-9
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
IEB, IRQB -- INTB Interrupt Enable/Request Flags
Bit Identifier
RESET
FB8H
3 "0" 0 R/W 1/4 Bits 3-2 0 Value
2 "0" 0 R/W 1/4
1 IEB 0 R/W 1/4
0 IRQB 0 R/W 1/4
Read/Write Bit Addressing .3-.2
Always logic zero
IEB
INTB Interrupt Enable Flag 0 1 Disable INTB interrupt requests Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag - Generate INTB interrupt (This bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
4-10
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
IET0, IRQT0 -- INTT0 Interrupt Enable/Request Flags
Bit Identifier
RESET
FBCH
3 "0" 0 R/W 1/4 Bits 3-2 0 Value
2 "0" 0 R/W 1/4
1 IET0 0 R/W 1/4
0 IRQT0 0 R/W 1/4
Read/Write Bit Addressing .3-.2
Always logic zero
IET0
INTT0 Interrupt Enable Flag 0 1 Disable INTT0 interrupt requests Enable INTT0 interrupt requests
IRQT0
INTT0 Interrupt Request Flag - Generate INTT0 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match.)
4-11
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
IEW, IRQW -- INTW Interrupt Enable/Request Flags
Bit Identifier
RESET
FBAH
3 "0" 0 R/W 1/4 Bits 3-2 0 Value
2 "0" 0 R/W 1/4
1 IEW 0 R/W 1/4
0 IRQW 0 R/W 1/4
Read/Write Bit Addressing .3-.2
Always logic zero
IEW
INTW Interrupt Enable Flag 0 1 Disable INTW interrupt requests Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag - Generate INTW interrupt (This bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.)
NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.
4-12
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
IMOD0 -- External Interrupt 0 (INT0) Mode Register
Bit Identifier
RESET
FB4H
3 .3 0 W 4 Value
2 "0" 0 W 4
1 .1 0 W 4
0 .0 0 W 4
Read/Write Bit Addressing .3
Interrupt Sampling Clock Selection Bit 0 1 Select CPU clock as a sampling clock Select sampling clock frequency of the selected system clock (fxx/64)
.2
Bit 2 0 Always logic zero
.1-.0
External Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Interrupt requests are triggered by a rising signal edge Interrupt requests are triggered by a falling signal edge Interrupt requests are triggered by both rising and falling signal edges Interrupt request flag (IRQ0) cannot be set to logic one
4-13
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
IMOD1 -- External Interrupt 1 (INT1) Mode Register
Bit Identifier
RESET
FB5H
3 "0" 0 W 4 Bits 3-1 0 Value
2 "0" 0 W 4
1 "0" 0 W 4
0 IMOD1.0 0 W 4
Read/Write Bit Addressing .3-.1
Always logic zero
.0
External Interrupt 1 Edge Detection Control Bit 0 1 Rising edge detection Falling edge detection
4-14
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
IMOD2 -- External Interrupt 2 (INT2) Mode Register
Bit Identifier
RESET
FB6H
3 "0" 0 W 4 Bits 3-2 0 Value
2 "0" 0 W 4
1 IMOD2.1 0 W 4
0 IMOD2.0 0 W 4
Read/Write Bit Addressing .3-.2
Always logic zero
.1-.0
External Interrupt 2 Edge Detection Selection Bit 0 0 1 1 0 1 0 1 Select rising edge at INT2 pin Reserved Select falling edge at KS2-KS3 Select falling edge at KS0-KS3
4-15
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
IPR -- Interrupt Priority Register
Bit Identifier
RESET
FB2H
1 .1 0 W 4 0 .0 0 W 4
3 IME 0 W 1/4 Value
2 .2 0 W 4
Read/Write Bit Addressing IME
Interrupt Master Enable Bit 0 1 Disable all interrupt processing Enable processing for all interrupt service requests
.2-.0
Interrupt Priority Assignment Bits 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Normal interrupt handling according to default priority settings Process INTB interrupt at highest priority Process INT0 interrupt at highest priority Process INT1 interrupt at highest priority Reserved Process INTT0 interrupt at highest priority
4-16
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
LCON -- LCD Output Control Register
Bit Identifier
RESET
F8EH
0 .0 0 W 4
3 "0" 0 W 4 Value
2 .2 0 W 4
1 "0" 0 W 4
Read/Write Bit Addressing
.3
LCD Bias Selection Bit 0 This bit is used for internal testing only; always logic zero.
.2
LCD Clock Output Disable/Enable Bit 0 1 Disable LCDCK and LCDSY signal outputs. Enable LCDCK and LCDSY signal outputs.
.1
Bit 1 0 Always logic zero
.0
LCD Display Control Bit 0 1 LCD output low, turns display off: cut off current to dividing resistor, and output port 8 latch contents. If LMOD.3 = "0": turn display off; output port 8 latch contents; If LMOD.3 = "1": COM and SEG output in display mode; LCD display on.
NOTES: 1. You can manipulate LCON.0, when you try to turn ON/OFF LCD display internally. If you want to control LCD ON/OFF or LCD contrast externally, you should set the LCON.0 to "0". refer to chapter 12, if you need more information. 2. To select the LCD bias, you must properly configure both LCON.0 and the external LCD bias circuit connection. 3. The LCON.3 register must be set to "0".
4-17
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
LMOD -- LCD Mode Register
Bit Identifier
RESET
F8DH, F8CH
6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 1/8 2 .2 0 W 8 1 .1 0 W 8 0 .0 0 W 8
7 .7 0 W 8 Value
Read/Write Bit Addressing .7-.6
LCD Output Segment and Pin Configuration Bits 0 0 1 1 0 1 0 1 Segments 24-27; and 28-31 Segment 24-27; 1-bit output at P8.4-P8.7 Segment 28-31; 1-bit output at P8.0-P8.3 1-bit output only at P8.0-P8.3, and P8.4-P8.7
.5-.4
LCD Clock (LCDCK) Frequency Selection Bits 0 0 1 1 0 1 0 1 fw/29 = 64 Hz fw/28 = 128 Hz fw/27 = 256 Hz fw/26 = 512 Hz
.3-.0
Duty and Bias Selection for LCD Display 0 1 1 1 1 1 - 0 0 0 0 1 - 0 0 1 1 0 - 0 1 0 1 0 LCD display off 1/4 duty, 1/3 bias 1/3 duty, 1/3 bias 1/2 duty, 1/2 bias 1/3 duty, 1/2 bias Static
NOTE: Watch timer frequency(fw) is assumed to be 32.768KHz.
4-18
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
PCON -- Power Control Register
Bit Identifier
RESET
FB3H
1 .1 0 W 4 0 .0 0 W 4
3 .3 0 W 4 Value
2 .2 0 W 4
Read/Write Bit Addressing .3-.2
CPU Operating Mode Control Bits 0 0 1 0 1 0 Enable normal CPU operating mode Initiate idle power-down mode Initiate stop power-down mode
.1-.0
CPU Clock Frequency Selection Bits 0 1 1 0 0 1 If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4
NOTE: 'fx' is the main system clock; 'fxt' is the subsystem clock.
4-19
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
PMG1 -- Port I/O Mode Flags (Group 1: Ports 3 and 6)
Bit Identifier
RESET
FE9H, FE8H
3 2 PM3.2 0 W 8 1 PM3.1 0 W 8 0 PM3.0 0 W 8
7 PM6.3 0 W 8 Value
6 PM6.2 0 W 8
5 PM6.1 0 W 8
4 PM6.0 0 W 8
PM3.3 0 W 8
Read/Write Bit Addressing PM6.3
P6.3 I/O Mode selection Flag 0 1 Set P6.3 to input mode Set P6.3 to output mode
PM6.2
P6.2 I/O Mode Selection Flag 0 1 Set P6.2 to input mode Set P6.2 to output mode
PM6.1
P6.1 I/O Mode Selection Flag 0 1 Set P6.1 to input mode Set P6.1 to output mode
PM6.0
P6.0 I/O Mode Selection Flag 0 1 Set P6.0 to input mode Set P6.0 to output mode
PM3.3
P3.3 I/O Mode Selection Flag 0 1 Set P3.3 to input mode Set P3.3 to output mode
PM3.2
P3.2 I/O Mode Selection Flag 0 1 Set P3.2 to input mode Set P3.2 to output mode
PM3.1
P3.1 I/O Mode Selection Flag 0 1 Set P3.1 to input mode Set P3.1 to output mode
PM3.0
P3.0 I/O Mode Selection Flag 0 1 Set P3.0 to input mode Set P3.0 to output mode
4-20
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
PMG2 -- Port I/O Mode Flags (Group 2: Port 2)
Bit Identifier
RESET
FEDH, FECH
3 "0" 0 W 8 2 PM2 0 W 8 1 "0" 0 W 8 0 "0" 0 W 8
7 "0" 0 W 8 Bits 7-3 0 Value
6 "0" 0 W 8
5 "0" 0 W 8
4 "0" 0 W 8
Read/Write Bit Addressing .7-.3
Always logic zero
PM2
P2 I/O Mode Selection Flag 0 1 Set P2 to input mode Set P2 to output mode
.1-.0
Bits 1-0 0 Always logic zero
4-21
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
PSW -- Program Status Word
Bit Identifier
RESET
FB1H, FB0H
6 5 SC1 0 R 8 4 SC0 0 R 8 3 IS1 0 R/W 1/4 2 IS0 0 R/W 1/4 1 EMB 0 R/W 1 0 ERB 0 R/W 1
7 C
(1)
SC2 0 R 8
Value
Read/Write Bit Addressing C
R/W
(2)
Carry Flag 0 1 No overflow or borrow condition exists An overflow or borrow condition exists
SC2-SC0
Skip Condition Flags 0 1 No skip condition exists; no direct manipulation of these bits is allowed A skip condition exists; no direct manipulation of these bits is allowed
IS1, IS0
Interrupt Status Flags 0 0 1 1 0 1 0 1 Service all interrupt requests Service only the high-priority interrupt(s) as determined in the interrupt priority register (IPR) Do not service any more interrupt requests Undefined
EMB
Enable Data Memory Bank Flag 0 1 Restrict program access to data memory to bank 15 (F80H-FFFH) and to the locations 000H-07FH in the bank 0 only Enable full access to data memory banks 0, 1, 2, and 15
ERB
Enable Register Bank Flag 0 1 Select register bank 0 as working register area Select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (SRB) instruction operand
NOTES: 1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during power-down mode (IDLE or STOP), the current value of the carry flag is retained. 2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for detailed information.
4-22
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
PUMOD -- Pull-Up Resistor Mode Register
Bit Identifier
RESET
FDDH, FDCH
4 "0" 0 W 8 3 PUR3 0 W 8 2 PUR2 0 W 8 1 PUR1 0 W 8 0 "0" 0 W 8
7 "0" 0 W 8 Bit 7 0 Value
6 PUR6 0 W 8
5 "0" 0 W 8
Read/Write Bit Addressing .7
Always logic zero
PUR6
Connect/Disconnect Port 6 Pull-Up Resistor Control Bit 0 1 Disconnect port 6 pull-up resistor Connect port 6 pull-up resistor
.5-.4
Bits 5-4 0 Always logic zero
PUR3
Connect/Disconnect Port 3 Pull-Up Resistor Control Bit 0 1 Disconnect port 3 pull-up resistor Connect port 3 pull-up resistor
PUR2
Connect/Disconnect Port 2 Pull-Up Resistor Control Bit 0 1 Disconnect port 2 pull-up resistor Connect port 2 pull-up resistor
PUR1
Connect/Disconnect Port 1 Pull-Up Resistor Control Bit 0 1 Disconnect port 1 pull-up resistor Connect port 1 pull-up resistor
.0
Bit 0 0 Always logic zero
NOTE: Pull-up resistors for all I/O ports are automatically disabled when they are configured to output mode.
4-23
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
SCMOD -- System Clock Mode Control Register
Bit Identifier
RESET
FB7H
0 .0 0 W 1
3 .3 0 W 1 Value
2 .2 0 W 1
1 "0" 0 W 1
Read/Write Bit Addressing .3, .2 and .0
CPU Clock Selection and Main System Clock Oscillation Control Bits 0 0 0 1 0 1 0 0 0 0 1 1 Select main system clock (fx); enable main system clock Select main system clock (fx); disable sub system clock Select sub system clock (fxt); enable main system clock Select sub system clock (fxt); disable main system clock
.1
Bit 1 0 Always logic zero
NOTE: SCMOD bits 3 and 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions.
4-24
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
TMOD0 -- Timer/Counter 0 Mode Register
Bit Identifier
RESET
F91H, F90H
4 .4 0 W 8 3 .3 0 W 1/8 2 .2 0 W 8 1 "0" 0 W 8 0 "0" 0 W 8
7 "0" 0 W 8 Bit 7 0 Value
6 .6 0 W 8
5 .5 0 W 8
Read/Write Bit Addressing .7
Always logic zero
.6-.4
Timer/Counter 0 Input Clock Selection Bits 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 External clock input at TCL0 pin on rising edge External clock input at TCL0 pin on falling edge Select clock: fxx/210 (4.09 kHz at 4.19 MHz) Select clock: fxx/28 (16.4 kHz at 4.19 MHz) Select clock: fxx/26 (65.5 kHz at 4.19 MHz) Select clock: fxx/24 (262 kHz at 4.19 MHz)
.3
Clear Counter and Resume Counting Control Bit 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is cleared automatically when counting starts.)
.2
Enable/Disable Timer/Counter 0 Bit 0 1 Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0
.1-.0
Bits 1-0 0 Always logic zero
4-25
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
TOE -- Timer Output Enable Flag Register
Bit Identifier
RESET
F92H
0 "u" - - -
3 "u" - - - Bit3 u Value
2 TOE0 0 R/W 1
1 "u" 0 - -
Read/Write Bit Addressing .3
Unknown value
TOE0
Timer/Counter 0 Output Enable Flag 0 1 Disable timer/counter 0 output at the TCLO0 pin Enable timer/counter 0 output at the TCLO0 pin
.1-.0
Bits 1-0 u Unknown value
NOTES: 1. "u" means that the bit is unknown.
4-26
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
WDFLAG -- Watchdog Timer Counter Clear Flag Register
Bit Identifier
RESET
F9AH
3 WDTCF 0 W 1/4 Value
2 "0" 0 W 1/4
1 "0" 0 W 1/4
0 "0" 0 W 1/4
Read/Write Bit Addressing WDTCF
Watchdog Timer Counter Clear Flag 1 Clears the watchdog timer counter
.2-.0
Bits 2-0 0 Always logic zero
NOTE: After watchdog timer is cleared by writing "1", this bit is cleared to "0" automatically. Instruction that clear the watchdog timer ("BITS WDTCF") should be executed at proper points in a program within a given period. If not executed within a given period and watchdog timer overflows, RESET signal is generated and system is restarted with reset status.
4-27
MEMORY MAP
KS57C2302/C2304/P2304 MICROCONTROLLER
WDMOD -- Watchdog Timer Mode Register
Bit Identifier
RESET
F99H, F98H
4 .4 0 W 8 3 .3 0 W 8 2 .2 1 W 8 1 .1 0 W 8 0 .0 1 W 8
7 .7 1 W 8 Value
6 .6 0 W 8
5 .5 1 W 8
Read/Write Bit Addressing WDMOD
Watchdog Timer Enable/Disable Control 5AH Any other value Disable watchdog timer function Enable watchdog timer function
4-28
KS57C2302/C2304/P2304 MICROCONTROLLER
MEMORY MAP
WMOD -- Watch Timer Mode Register
Bit Identifier
RESET
F89H, F88H
4 .4 0 W 8 3 .3
(note)
7 .7 0 W 8 Value
6 "0" 0 W 8
5 .5 0 W 8
2 .2 0 W 8
1 .1 0 W 8
0 .0 0 W 8
Read/Write Bit Addressing .7
R 1
Enable/Disable Buzzer Output Bit 0 1 Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output
.6
Bit 6 0 Always logic zero
.5-.4
Output Buzzer Frequency Selection Bits 0 0 1 1 0 1 0 1 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output
.3
XTin Input Level Control Bit 0 1 Input level to XTin pin is low; 1-bit read-only addressable for tests Input level to XTin pin is high; 1-bit read-only addressable for tests
.2
Enable/Disable Watch Timer Bit 0 1 Disable watch timer and clear frequency dividing circuits Enable watch timer
.1
Watch Timer Speed Control Bit 0 1 Normal speed; set IRQW to 0.5 seconds High-speed operation; set IRQW to 3.91 ms
.0
Watch Timer Clock Selection Bit 0 1 Select system clock (fxx)/128 as the watch timer clock Select a subsystem clock as the watch timer clock
NOTE: RESET sets WMOD.3 to the current input level of the subsystem clock, XTin. If the input level is high, WMOD.3 is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.
4-29
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
5
SAM47 INSTRUCTION SET
OVERVIEW The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction operand in place of the actual address. Other important features of the SAM47 instruction set include: -- 1-byte referencing of long instructions (REF instruction) -- Redundant instruction reduction (string effect) -- Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple operand formats. Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb, b, and so on. Using instruction labels can greatly simplify program writing and debugging tasks. INSTRUCTION SET FEATURES In this Chapter, the following SAM47 instruction set features are described in detail: -- Instruction reference area -- Instruction redundancy reduction -- Flexible bit manipulation -- ADC and SBC instruction skip condition NOTE The ROM size accessed by instruction may change for KS57C2302 and KS57C2304.
5-1
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Instruction Reference Area Using the 1-byte REF (Reference) instruction, you can reference instructions stored in addresses 0020H-007FH of program memory (the REF instruction look-up table). The location referenced by REF may contain either two 1-byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must always be an even number. 3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte instructions, the 2-byte pseudo commands TJP and TCALL must be written in the reference. The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction execution sequence resumes at the address immediately following the REF instruction. By using REF instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the program size. To summarize, the REF instruction can be used in three ways: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions; -- Branching to any location by referencing a branch address that is stored in the look-up table; -- Calling subroutines at any location by referencing a call address that is stored in the look-up table. If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions. Two-byte instructions can be referenced by using a REF instruction. (An exception is XCH A,DA*) If the MSB value of the first 1-byte instruction in the reference area is "0", the instruction cannot be referenced by a REF instruction. Therefore, if you use REF to reference two 1-byte instructions stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. These combinations are described in Table5-1. Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups First 1-Byte Instruction Instruction LD Operand A,#im Second 1-Byte Instruction Instruction INCS* INCS DECS* LD A,@RRq INCS* INCS DECS* LD @HL,A INCS* INCS DECS* Operand R RRb R R RRb R R RRb R
NOTE: If the MSB value of the first one-byte binary code in instruction is "0", the instruction cannot be referenced by a REF instruction.
5-2
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Reducing Instruction Redundancy When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also ignored. In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows it is interpreted as redundant and is ignored: LD LD A,#im EA,#imm ; Load 4-bit immediate data (#im) to accumulator ; Load 8-bit immediate data (#imm) to extended ; accumulator
In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored: BITR LD LD LD LD EMB A,#1H A,#2H A,#3H 23H,A ; ; ; ; Execute instruction Ignore, redundant instruction Ignore, redundant instruction Execute instruction, 023H #1H
If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are detected, only the first LD is executed and the LDs which immediately follow are ignored. For example, LD LD LD LD LD HL,#10H HL,#20H A,#3H EA,#35H @HL,A ; ; ; ; ; HL 10H Ignore, redundant instruction A 3H Ignore, redundant instruction (10H) 3H
If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply: -- If the instruction preceding the REF has a redundancy effect, this effect is canceled and the referenced instruction is not skipped. -- If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped.
+ PROGRAMMING TIP -- Example of the Instruction Redundancy Effect
ABC ORG LD ORG * * * LD REF * * * REF LD 0020H EA,#30H 0080H ; Stored in REF instruction reference area
EA,#40H ABC
; Redundancy effect is encountered ; No skip (EA #30H)
ABC EA,#50H
; EA #30H ; Skip
5-3
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear, the SAM47 instruction set can also perform bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit addressing modes. Three types of bit addressing are supported: -- mema.b -- memb.@L -- @H+DA.b The parameters of these bit addressing modes are described in more detail in Table 5-2.
Table 5-2. Bit Addressing Modes and Parameters Addressing Mode mema.b memb.@L @H+DA.b Addressable Peripherals ERB, EMB, IS1, IS0, IEx, IRQx Ports 1, 2, 3, 6 Ports 1, 2, 3, 6, and BSC All bit-manipulable peripheral hardware FB0H-FBFH FF0H-FFFH FC0H-FFFH All bits of the memory bank specified by EMB and SMB that are bit-manipulable Address Range
Instructions Which Have Skip Conditions The following instructions have a skip function when an overflow or borrow occurs: XCHI XCHD LDI LDD INCS DECS ADS SBS
If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. However, the carry flag value is unaffected. The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. Instructions Which Affect the Carry Flag The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: ADC SBC SCF RCF CCF LDB BAND BOR BXOR C,(operand) C,(operand) C,(operand) C,(operand)
5-4
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
ADC and SBC Instruction Skip Conditions The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ADS A,#im'. If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If, however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and 'SBC A,@HL' skip feature. Table 5-3. Skip Conditions for ADC and SBC Instructions Sample Instruction Sequences ADC A,@HL ADS A,#im xxx xxx SBC A,@HL ADS A,#im xxx xxx 1 2 3 4 1 2 3 4 If the result of instruction 1 is: Overflow No overflow Borrow No borrow Then, the execution sequence is: 1, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 3, 4 Reason ADS cannot skip instruction 3, even if it has a skip function. ADS cannot skip instruction 3, even if it has a skip function.
5-5
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
SYMBOLS and CONVENTIONS Table 5-4. Data Type Symbols Symbol d a b r f i t Data Type Immediate data Address data Bit data Register data Flag data Indirect addressing data memc x 0.5 immediate data @ src dst (R) .b im imm # Table 5-5. Register Identifiers Full Register Name 4-bit accumulator 4-bit working registers 8-bit extended accumulator 8-bit memory pointer 8-bit working registers Select register bank 'n' Select memory bank 'n' Carry flag Program status word Port 'n' 'm'-th bit of port 'n' Interrupt priority register Enable memory bank flag Enable register bank flag A E, L, H, X, W, Z, Y EA HL WX, YZ, WL SRB n SMB n C PSW Pn Pn.m IPR EMB ERB SB XOR OR AND [(RR)] ID ADR ADRn R Ra RR RRa RRb RRc mema memb memc Table 5-6. Instruction Operand Notation Symbol DA Definition Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 000H-1FFFH immediate address 'n' bit address A, E, L, H, X, W, Z, Y E, L, H, X, W, Z, Y EA, HL, WX, YZ HL, WX, WL HL, WX, YZ WX, WL FB0H-FBFH, FF0H-FFFH FC0H-FFFH Code direct addressing: 0020H-007FH Select bank register (8 bits) Logical exclusive-OR Logical OR Logical AND Contents addressed by RR
5-6
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
OPCODE DEFINITIONS Table 5-7. Opcode Definitions (Direct) Register A E L H X W Z Y EA HL WX YZ r2 0 0 0 0 1 1 1 1 0 0 1 1 r1 0 0 1 1 0 0 1 1 0 1 0 1 r0 0 1 0 1 0 1 0 1 0 0 0 0 Table 5-8. Opcode Definitions (Indirect) Register @HL @WX @WL i2 1 1 1 i1 0 1 1 i0 1 0 1
i = Immediate data for indirect addressing
r = Immediate data for register
CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected using the PCON register. In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped -- whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB instructions. The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows: Case 1: No skip Case 2: Skip is 1-byte or 2-byte instruction Case 3: Skip is 3-byte instruction S = 0 cycles S = 1 cycle S = 2 cycles
NOTE: REF instructions are skipped in one machine cycle.
5-7
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
HIGH-LEVEL SUMMARY This Chapter contains a high-level summary of the SAM47 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category. These tables are a useful quick-reference resource when writing application programs. If you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Brief operation description -- Number of bytes of the instruction and operand(s) -- Number of machine cycles required to execute the instruction The tables in this Chapter are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions
5-8
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Table 5-9. CPU Control Instructions -- High-Level Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand Operation Description Set carry flag to logic one Reset carry flag to logic zero Complement carry flag Enable all interrupts Disable all interrupts Engage CPU idle mode Engage CPU stop mode No operation Select memory bank Select register bank Reference code Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location Bytes 1 1 1 2 2 2 2 1 2 2 1 2 Cycles 1 1 1 2 2 2 2 1 2 2 3 2
Table 5-10. Program Control Instructions -- High-Level Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR JP JPS JR ADR12 ADR12 #im @WX @EA CALL CALLS RET IRET SRET ADR12 ADR11 - - - Operation Description Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Jump to direct address (12 bits) Jump direct in page (12 bits) Jump to immediate address Branch relative to WX register Branch relative to EA Call direct address (12 bits) Call direct address within 2 K (11 bits) Return from subroutine Return from interrupt Return from subroutine and skip Bytes 2 2 2 1 2 2 3 2 1 2 2 3 2 1 1 1 Cycles 2+S 2+S 2+S 1+S 2+S 2+S 3 2 2 3 3 4 3 3 3 3+S
5-9
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-11. Data Transfer Instructions -- High-Level Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH POP A,@HL A,@HL EA,@WX EA,@EA A RR SB RR SB Operation Description Exchange A and direct data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Exchange A and indirect data memory contents; increment contents of register L and skip on carry Exchange A and indirect data memory contents; decrement contents of register L and skip on carry Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Load indirect data memory to A; increment register L contents and skip on carry Load indirect data memory contents to A; decrement register L contents and skip on carry Load code byte from WX to EA Load code byte from EA to EA Rotate right through carry bit Push register pair onto stack Push SMB and SRB values onto stack Pop to register pair from stack Pop SMB and SRB values from stack Bytes 2 1 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 1 1 1 1 1 1 2 1 2 Cycles 2 1 1 2 2 2 2+S 2+S 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 2+S 2+S 3 3 1 1 2 1 2
5-10
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Table 5-12. Logic Instructions -- High-Level Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A Operation Description Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Complement accumulator (A) Bytes 2 1 2 2 2 1 2 2 2 1 2 2 2 Cycles 2 1 2 2 2 1 2 2 2 1 2 2 2
Table 5-13. Arithmetic Instructions -- High-Level Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS INCS R RR R DA @HL RRb Operation Description Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Add 4-bit immediate data to A and skip on carry Add 8-bit immediate data to EA and skip on carry Add indirect data memory to A and skip on carry Add register pair (RR) contents to EA and skip on carry Add EA to register pair (RRb) and skip on carry Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 1 2 2 1 Cycles 1 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1+S 2+S 1+S 2+S 2+S 1+S
5-11
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-14. Bit Manipulation Instructions -- High-Level Summary Name BTST C DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b BOR C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b LDB mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load specified memory bit to carry bit Load specified indirect memory bit to carry bit Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Exclusive-OR carry with specified memory bit Logical-OR carry with specified memory bit Logical-AND carry flag with specified memory bit Clear specified memory bit to logic zero Set specified memory bit 2 2 Test specified bit; skip and clear if memory bit is set Test specified memory bit and skip if bit equals "0" Operand Operation Description Test specified bit and skip if carry flag is set Test specified bit and skip if memory bit is set Bytes 1 2 Cycles 1+S 2+S
5-12
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BINARY CODE SUMMARY This Chapter contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM47 instruction set. The same binary values and notation are also included in the detailed descriptions of individual instructions later in Chapter 5. If you are reading this user's manual for the first time, please just scan this very detailed information briefly. Most of the general information you will need to write application programs can be found in the high-level summary tables in the previous Chapter. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Binary values -- Operation notation The tables in this Chapter are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions
5-13
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-15. CPU Control Instructions -- Binary Code Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 t7 E M B 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 t6 E R B 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 t5 0
Binary Code
0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 t4 0 0 0 0 1 0 1 0 1 0 1 0 0 1 d3 1 0 t3 1 1 1 1 0 1 0 1 0 1 0 0 1 d2 1 0 t2 1 1 1 1 1 1 1 1 1 1 1 0 0 d1 0 d1 t1 a9 1 0 0 1 0 0 0 1 1 1 1 0 1 d0 1 d0 t0 a8
Operation Notation C1 C0 CC IME 1 IME 0 PCON.2 1 PCON.3 1 No operation SMB n (n = 0, 1, 15) SRB n (n = 0, 1, 2, 3) PC11-0 = memc7-4, memc3-0 <1 ROM (2 x n) 7-6 EMB, ERB ROM (2 x n) 5-4 0 ROM (2 x n) 3-0 PC11-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7)
a11 a10
a7
a6
a5
a4
a3
a2
a1
a0
5-14
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Table 5-16. Program Control Instructions -- Binary Code Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR JP ADR12
1 d3 1 0 1 0 0 1 0 1 1 1 0 a7 1 d2 1 1 1 1 0 1 0 1 1 1 0 a6 0 a6 0 d1 0 1 0 1 1 0 0 0 1 0 0 a5 0 a5
Binary Code
1 d0 1 1 1 0 1 1 0 1 0 1 0 a4 1 a4 1 0 1 d3 1 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 0 r1 0 d1 0 r1 0 0 0 0 r1 1 a9 a1 a9 a1 1 r0 1 d0 1 r0 0 0 1 0 0 1 a8 a0 a8 a0
Operation Notation Skip if R = im Skip if (HL) = im Skip if A = R Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if EA = RR PC11-0 ADR12
a11 a10 a3 a2
JPS JR
ADR12 #im * @WX @EA
1 a7
a11 a10 a3 a2
PC11-0 ADR12 PC11-0 ADR (PC-15 to PC+16)
1 0 1 0
1 1 1 1 1 1 a6 1
0 1 0 1 0 0 a5 1
1 0 1 0 1 0 a4 0
1 0 1 0 1
1 1 1 0 0
0 0 0 0 1 a9 a1 a9
1 0 1 0 1 a8 a0 a8
PC11-0 PC11-8 + (WX) PC11-0 PC11-8 + (EA) [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC11-8 SP SP - 6 PC11-0 ADR12 [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC11-8 SP SP - 6 PC11 0 PC10-0 ADR11
CALL
ADR12
1 0 a7
a11 a10 a3 1 a2 a10
CALLS
ADR11
1
a7
a6
a5
a4
a3
a2
a1
a0
First Byte
Condition
a2 a2 a1 a1 a0 a0
* JR #im
0 0
0 0
0 0
1 0
a3 a3
PC PC+2 to PC+16 PC PC-1 to PC-15
5-15
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-16. Program Control Instructions -- Binary Code Summary (Continued) Name RET Operand -
1 1 0
Binary Code
0 0 1 0 1
Operation Notation PC11-8 (SP + 1) (SP) PC7-0 (SP + 2) (SP + 3) EMB,ERB (SP + 5) (SP + 4) SP SP + 6 PC11-8 (SP + 1) (SP) PC7-0 (SP + 2) (SP + 3) PSW (SP + 4) (SP + 5) SP SP + 6 PC11-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 5) (SP + 4) SP SP + 6, then skip
IRET
-
1
1
0
1
0
1
0
1
SRET
-
1
1
1
0
0
1
0
1
Table 5-17. Data Transfer Instructions -- Binary Code Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra
0 a7 0 0 1 a7 1 1 1 0 0 0 1 1 1 a7 1 0 1 a6 1 1 1 a6 1 1 1 0 1 1 0 0 0 a6 1 0 1 a5 1 1 0 a5 0 1 0 0 1 1 1 0 0 a5 0 0
Binary Code
1 a4 0 1 0 a4 1 0 1 0 1 1 1 0 0 a4 1 0 1 a3 1 1 1 a3 1 0 1 0 1 1 d3 1 1 a3 1 1 0 a2 r2 i2 1 a2 1 r2 1 0 0 0 d2 i2 1 a2 1 r2 0 a1 r1 i1 1 a1 0 r1 0 0 1 1 d1 i1 0 a1 0 r1 1 a0 r0 i0 1 a0 0 0 0 1 0 1 d0 i0 0 a0 1 r0
Operation Notation A DA A Ra A (RRa) A DA,E DA + 1 EA RRb A (HL), E (HL + 1) A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH A im A (RRa) A DA A Ra
5-16
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Table 5-17. Data Transfer Instructions -- Binary Code Summary (Continued) Name LD Operand Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH A,@HL A,@HL EA,@WX EA,@EA A RR SB
1 d3 1 d7 1 a7 1 0 1 0 1 a7 1 1 1 1 a7 1 1 1 0 1 1 1 1 1 0 1 0 1 d2 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6 1 1 1 0 0 0 1 1 0 0 1 1 0 d1 0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5 0 1 0 0 0 0 0 0 0 1 0 1
Binary Code
1 d0 0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 d3 1 a3 1 0 1 1 1 a3 1 1 0 1 a3 1 0 1 0 1 1 1 1 1 1 1 0 0 r2 r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2 1 r2 1 0 0 0 1 0 0 r2 1 1 0 r1 r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1 0 r1 0 0 1 1 0 0 0 r1 0 1 1 r0 1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0 0 0 0 0 0 1 0 0 0 1 1 1
Operation Notation Ra im RR imm DA A Ra A A (HL), E (HL + 1) A DA, E DA + 1 EA RRb (HL) A DA A, DA + 1 E RRb EA (HL) A, (HL + 1) E A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH EA [PC11-8 + (WX)] EA [PC11-8 + (EA)] C A.0, A3 C A.n-1 A.n (n = 1, 2, 3) ((SP-1)) ((SP-2)) (RR), (SP) (SP)-2 ((SP-1)) (SMB), ((SP-2)) (SRB), (SP) (SP)-2
5-17
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-17. Data Transfer Instructions -- Binary Code Summary (Concluded) Name POP Operand RR SB
0 1 0 0 1 1 1 0 1
Binary Code
0 1 0 1 1 0 r2 1 1 r1 0 1 0 1 0
Operation Notation RRL (SP), RRH (SP + 1) SP SP + 2 (SRB) (SP), SMB (SP + 1), SP SP + 2
Table 5-18. Logic Instructions -- Binary Code Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A
1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1
Binary Code
1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d3 1 1 1 1 0 1 d3 1 1 0 1 0 1 1 1 d2 0 1 r2 1 r2 1 d2 0 1 r2 1 r2 1 d2 0 1 r2 1 r2 1 1 0 d1 0 0 r1 0 r1 0 d1 1 0 r1 0 r1 0 d1 1 0 r1 0 r1 0 1 1 d0 1 0 0 0 0 1 d0 0 0 0 0 0 1 d0 1 0 0 0 0 1 1
Operation Notation A A AND im A A AND (HL) EA EA AND RR RRb RRb AND EA A A OR im A A OR (HL) EA EA OR RR RRb RRb OR EA A A XOR im A A XOR (HL) EA EA XOR (RR) RRb RRb XOR EA AA
5-18
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Table 5-19. Arithmetic Instructions -- Binary Code Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS R RR INCS R DA @HL RRb
0 1 1 1 1 1 1 d7 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 a7 1 0 1 0 1 0 1 0 0 1 d6 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 a6 1 1 0 1 0 1 0 1 1 0 d5 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 a5 0 1 0
Binary Code
1 1 0 1 0 0 0 d4 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 a4 1 0 0 1 1 1 1 0 d3 1 d3 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 a3 1 0 0 1 1 r2 1 r2 d2 0 d2 1 1 r2 1 r2 1 1 r2 1 r2 1 1 r2 1 r2 r2 1 r2 r2 0 a2 1 0 r2 1 0 r1 0 r1 d1 0 d1 1 0 r1 0 r1 0 0 r1 0 r1 0 0 r1 0 r1 r1 0 r1 r1 1 a1 0 1 r1 0 0 0 0 0 d0 1 d0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 r0 0 0 r0 0 a0 1 0 0
Operation Notation C, A A + (HL) + C C, EA EA + RR + C C, RRb RRb + EA + C A A + im; skip on carry EA EA + imm; skip on carry A A+ (HL); skip on carry EA EA + RR; skip on carry RRb RRb + EA; skip on carry C,A A - (HL) - C C, EA EA -RR - C C,RRb RRb - EA - C A A - (HL); skip on borrow EA EA - RR; skip on borrow RRb RRb - EA; skip on borrow R R-1; skip on borrow RR RR-1; skip on borrow R R + 1; skip on carry DA DA + 1; skip on carry (HL) (HL) + 1; skip on carry RRb RRb + 1; skip on carry
5-19
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary Name BTST C DA.b mema.b * memb.@L Operand
1 1 a7 1 1 1 a6 1 0 b1 a5 1
Binary Code
1 b0 a4 1 0 0 a3 1 1 0 a2 0 1 1 a1 0 1 1 a0 1
Operation Notation Skip if C = 1 Skip if DA.b = 1 Skip if mema.b = 1
1 0
1 1 1 0 1 a6 1
1 0 1 b1 b1 a5 1
1 0 1 b0 b0 a4 1
1 a5 1 a3 0 a3 1
0 a4 0 a2 0 a2 0
0 a3 0 a1 1 a1 0
1 a2 1 a0 0 a0 0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 Skip if [H + DA.3-0].b = 1 Skip if DA.b = 0 Skip if mema.b = 0
@H+DA.b BTSF DA.b mema.b * memb.@L
1 0 1 a7 1
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 1
0 a4 0 a2 1
0 a3 0 a1 0
0 a2 0 a0 1
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0 Skip if [H + DA.3-0].b = 0 Skip if mema.b = 1 and clear
@H DA.b BTSTZ mema.b * memb.@L
1 0 1
1 0
1 1 1 0 1 a6 1
1 0 1 b1 b1 a5 1
1 0 1 b0 b0 a4 1
1 a5 1 a3 0 a3 1
1 a4 1 a2 0 a2 1
0 a3 0 a1 0 a1 1
1 a2 1 a0 1 a0 1
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear Skip if [H + DA.3-0].b =1 and clear DA.b 1 mema.b 1 [memb.7-2 + L.3-2].b [L.1-0] 1 [H + DA.3-0].b 1
@H+DA.b BITS DA.b mema.b * memb.@L @H+DA.b
1 0 1 a7 1
1 0 1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
5-20
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Continued) Name BITR Operand DA.b mema.b * memb.@L @H+DA.b BAND C,mema.b * C,memb.@L
1 a7 1 1 a6 1 b1 a5 1
Binary Code
b0 a4 1 0 a3 1 0 a2 1 0 a1 1 0 a0 0
Operation Notation DA.b 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 C C AND mema.b C C AND [memb.7-2 + L.3-2]. [L.1-0] C C AND [H + DA.3-0].b C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b
1 0 1 0 1
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
1 a3 1 a1 0
0 a2 0 a0 1
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
0 a5 0 a3 0
1 a4 1 a2 1
0 a3 0 a1 1
1 a2 1 a0 0
C,@H+DA.b BOR C,mema.b * C,memb.@L
1 0 1
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
0 a5 0 a3 0
1 a4 1 a2 1
1 a3 1 a1 1
0 a2 0 a0 1
C,@H+DA.b BXOR C,mema.b * C,memb.@L
1 0 1
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses
a2 a2 a1 a1 a0 a0
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
FB0H-FBFH FF1H-FF9H
5-21
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Concluded) Name LDB Operand mema.b,C * memb.@L,C @H+DA.b,C C,mema.b * C,memb.@L C,@H+DA.b
1 1 1
Binary Code
1 1 1 0 0
Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H + [DA.3-0].b (C) C mema.b C memb.7-2 + [L.3-2] . [L.1-0] C [H + DA.3-0].b
1 0 1 0 1
1 1 1 b2 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
0 a3 0 a1 0
0 a2 0 a0 0
1 0 1 0
1 1 1 b2
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
0 a3 0 a1
0 a2 0 a0
Second Byte
Bit Addresses
a2 a2 a1 a1 a0 a0
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
FB0H-FBFH FF0H-FFFH
5-22
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction of the SAM47 instruction set. Information is arranged in a consistent format to improve readability and for use as a quickreference resource for application programmers. If you are reading this user's manual for the first time, please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set. The information elements of the instruction description format are as follows: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Operation overview (from the "High-Level Summary" table) -- Textual description of the instruction's effect -- Binary code overview (from the "Binary Code Summary" table) -- Programming example(s) to show how the instruction is used
5-23
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
ADC -- Add With Carry
ADC Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2
Description:
The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. (This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an 'ADS A,#im' instruction, the next instruction will not be skipped.) Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 1 0 r1 0 r1 0 0 0 0 0 C, RRb RRb + EA + C Operation Notation C, A A + (HL) + C C, EA EA + RR + C
Examples:
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF ADC JPS ; C "1" ; EA 0C3H + 0AAH + 1H = 6EH, C "1" ; Jump to XXX; no skip after ADC
EA,HL XXX
2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF ADC JPS ; C "0" ; EA 0C3H + 0AAH + 0H = 6EH, C "1" ; Jump to XXX; no skip after ADC
EA,HL XXX
5-24
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
ADC -- Add With Carry
ADC Examples: (Continued) 3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction immediately after the ADS. An ADS instruction immediately after the ADC does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A 7H, C "1" Skip this instruction because C = "1" after ADC result
A,#8H A,#6H A,@HL A,#0AH XXX
b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS ; A,#3H A,#6H A,@HL A,#0AH C ; ; ; ; ; ; "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.)
JPS
XXX
5-25
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
ADS -- Add And Skip On Overflow
ADS Operation: dst,src Operand A, #im EA,#imm A,@HL EA,RR RRb,EA Operation Summary Add 4-bit immediate data to A and skip on overflow Add 8-bit immediate data to EA and skip on overflow Add indirect data memory to A and skip on overflow Add register pair (RR) contents to EA and skip on overflow Add EA to register pair (RRb) and skip on overflow Bytes 1 2 1 2 2 Cycles 1+S 2+S 1+S 2+S 2+S
Description:
The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an ADS instruction, the next instruction is not skipped. Operand A, #im EA,#imm A,@HL EA,RR RRb,EA 1 1 d7 0 1 1 1 1 0 1 d6 0 1 0 1 0 1 0 d5 1 0 0 0 0 Binary Code 0 0 d4 1 1 1 1 1 d3 1 d3 1 1 1 1 0 d2 0 d2 1 1 r2 1 r2 d1 0 d1 1 0 r1 0 r1 d0 1 d0 1 0 0 0 0 RRb RRb + EA; skip on overflow A A + (HL); skip on overflow EA EA + RR; skip on overflow Operation Notation A A + im; skip on overflow EA EA + imm; skip on overflow
Examples:
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag = "0": ADS JPS JPS EA,HL XXX YYY ; ; ; ; EA 0C3H + 0AAH = 6DH, C "0" ADS skips on overflow, but carry flag value is not affected. This instruction is skipped since ADS had an overflow. Jump to YYY.
5-26
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
ADS -- Add And Skip On Overflow
ADS Examples: (Continued) 2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and the carry flag = "0": ADS JPS EA,HL XXX ; EA 0C3H + 12H = 0D5H, C "0" ; Jump to XXX; no skip after ADS.
3. If 'ADC A,@HL' is followed by an 'ADS A,#im', the ADC skips on overflow to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'ADC A,@HL' does not skip even if overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A 7H, C "1" Skip this instruction because C = "1" after ADC result.
A,#8H A,#6H A,@HL A,#0AH XXX
b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.)
A,#3H A,#6H A,@HL A,#0AH
JPS
XXX
5-27
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
AND -- Logical And
AND Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
The source operand is logically ANDed with the destination operand. The result is stored in the destination. The logical AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both "1"; otherwise a "0" bit is stored. The contents of the source are unaffected. Operand A,#im A,@HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 0 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb AND EA A A AND (HL) EA EA AND RR Operation Notation A A AND im
Example:
If the extended accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction AND EA,HL
leaves the value 41H (01000001B) in the extended accumulator EA .
5-28
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BAND -- Bit Logical And
BAND Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-AND carry flag with memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. The bit value of the source operand is not affected. Operand C,mema.b * C,memb.@L 1 1 1 Binary Code 1 0 1 0 1 Operation Notation C C AND mema.b C C AND [memb.7-2 + L.3- 2]. [L.1-0] C C AND [H + DA.3-0].b
1
1
1
1
0
1
0
1
0 C,@H+DA.b 1 0
1 1 0
0 1 b1
0 1 b0
a5 0 a3
a4 1 a2
a3 0 a1
a2 1 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. The following instructions set the carry flag if P1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): SMB BAND 15 C,P1.0 ; C "1" ; If P1.0 = "1", C "1" ; If P1.0 = "0", C "0"
2. Assume the P1 address is FF1H and the value for register L is 9H (1001B). The address (memb.7-2) is 111100B; (L.3-2) is 10B. The resulting address is 11110010B or FF2H, specifying P2. The bit value for the BAND instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P2.1: LD BAND L,#9H C,P1.@L ; P1.@L is specified as P2.1 ; C AND P2.1
5-29
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BAND -- Bit Logical And
BAND Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG (3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BAND EQU 20H.3 H,#2H C,@H+FLAG
; C AND FLAG (20H.3)
5-30
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BITR -- Bit Reset
BITR Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Clear specified memory bit to logic zero Bytes 2 2 2 2 Cycles 2 2 2 2
Description:
A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No other bits in the destination are affected. Operand DA.b mema.b * memb.@L @H+DA.b 1 a7 1 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 1 0 a1 1 0 a0 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 Operation Notation DA.b 0
1 0 1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
0 a2 0 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. Bit location 30H.2 in the RAM has a current value of logic one. The following instruction clears the third bit in RAM location 30H (bit 2) to logic zero: BITR 30H.2 ; 30H.2 "0"
2. You can use BITR in the same way to manipulate a port address bit: BITR P2.0 ; P2.0 "0"
5-31
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BITR -- Bit Reset
BITR Examples: (Continued) 3. Assuming that P2.2, P2.3, and P3.0-P3.3 are cleared to "0": BP2 LD BITR INCS JR L,#0AH P1.@L L BP2 ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
4. If bank 0, location 0A0H.0 is cleared (and regardless of whether the EMB value is logic zero), BITR has the following effect: FLAG EQU * * * BITR * * * LD BITR 0A0H.0
EMB
H,#0AH @H+FLAG
; Bank 0 (AH + 0H).0 = 0A0H.0 "0"
NOTE: Since the BITR instruction is used for output functions, the pin names used in the examples above may change for different devices in the SAM47 product family.
5-32
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BITS -- Bit Set
BITS Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Set specified memory bit Bytes 2 2 2 2 Cycles 2 2 2 2
Description:
This instruction sets the specified bit within the destination without affecting any other bits in the destination. BITS can manipulate any bit that is addressable using direct or indirect addressing modes. Operand DA.b mema.b * memb.@L @H+DA.b 1 a7 1 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 1 0 a1 1 1 a0 1 mema.b 1 [memb.7-2 + L.3-2].b [L.1-0] 1 [H + DA.3-0].b 1 Operation Notation DA.b 1
1 0 1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. Assuming that bit location 30H.2 in the RAM has a current value of "0", the following instruction sets the second bit of location 30H to "1". BITS 30H.2 ; 30H.2 "1"
2. You can use BITS in the same way to manipulate a port address bit: BITS P2.0d ; P2.0 "1"
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BITS -- Bit Set
BITS Examples: (Continued) 3. Given that P2.2, P2.3, and P3.0-P3.3 are set to "1": BP2 LD BITS INCS JR L,#0AH P1.@L L BP2 ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
4. If bank 0, location 0A0H.0, is set to "1" and the EMB = "0", BITS has the following effect: FLAG EQU * * * BITR * * * LD BITS 0A0H.0
EMB
H,#0AH @H+FLAG
; Bank 0 (AH + 0H).0 = 0A0H.0 "1"
NOTE: Since the BITS instruction is used for output functions, pin names used in the examples above may change for different devices in the SAM47 product family.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BOR -- Bit Logical OR
BOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-OR carry with specified memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically ORed with the carry flag bit value. The value of the source is unaffected. Operand C,mema.b * C,memb.@L 1 1 1 Binary Code 1 0 1 1 0 Operation Notation C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
0 a2 0 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. The carry flag is logically ORed with the P1.0 value: RCF BOR ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0"
C,P1.0
2. The P1 address is FF1H and register L contains the value 9H (1001B). The address (memb.7- 2) is 111100B and (L.3-2) = 10B. The resulting address is 11110010B or FF2H, specifying P2. The bit value for the BOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P2.1: LD BOR L,#9H C,P1.@L ; P1.@L is specified as P2.1; C OR P2.1
5-35
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BOR -- Bit Logical OR
BOR Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BOR EQU 20H.3 H,#2H C,@H+FLAG
; C OR FLAG (20H.3)
5-36
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BTSF -- Bit Test and Skip on False
BTSF Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Test specified memory bit and skip if bit equals "0" Bytes 2 2 2 2 Cycles 2+S 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips the instruction which immediately follows it; otherwise the instruction following the BTSF is executed. The destination bit value is not affected. Operand DA.b mema.b * memb.@L 1 a7 1 1 0 @H + DA.b 1 0 1 a6 1 1 1 1 0 b1 a5 1 1 0 1 b1 Binary Code b0 a4 1 1 0 1 b0 0 a3 1 1 a5 1 a3 0 a2 0 0 a4 0 a2 1 a1 0 0 a3 0 a1 0 a0 0 0 a2 0 a0 Skip if [H + DA.3-0].b = 0 Skip if mema.b = 0 Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0 Operation Notation Skip if DA.b = 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. If RAM bit location 30H.2 is set to logic zero, the following instruction sequence will cause the program to continue execution from the instruction identified as LABEL2: BTSF RET JP 30H.2 LABEL2 ; If 30H.2 = "0", then skip ; If 30H.2 = "1", return
2. You can use BTSF in the same way to manipulate a port pin address bit: BTSF RET JP P2.0 LABEL3 ; If P2.0 = "0", then skip ; If P2.0 = "1", then return
5-37
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BTSF -- Bit Test and Skip on False
BTSF Examples: (Continued) 3. P2.2, P2.3 and P3.0-P3.3 are tested: BP2 LD BTSF RET INCS JR L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
L BP2
4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTSF has the following effect: FLAG EQU * * * BITR * * * LD BTSF RET * * * 0A0H.0
EMB
H,#0AH @H+FLAG
; If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip
5-38
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BTST -- Bit Test and Skip on True
BTST Operation: C DA.b mema.b memb.@L @H+DA.b dst.b Operand Operation Summary Test carry bit and skip if set (= "1") Test specified bit and skip if memory bit is set Bytes 1 2 2 2 2 Cycles 1+S 2+S 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is "1", the instruction that immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST instruction is executed. The destination bit value is not affected. Operand C DA.b mema.b * memb.@L 1 1 a7 1 1 1 a6 1 0 b1 a5 1 Binary Code 1 b0 a4 1 0 0 a3 1 1 0 a2 0 1 1 a1 0 1 1 a0 1 Skip if mema.b = 1 Operation Notation Skip if C = 1 Skip if DA.b = 1
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
0 a4 0 a2
0 a3 0 a1
1 a2 1 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 Skip if [H + DA.3-0].b = 1
@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. If RAM bit location 30H.2 is set to logic zero, the following instruction sequence will execute the RET instruction: BTST RET JP 30H.2 LABEL2 ; If 30H.2 = "1", then skip ; If 30H.2 = "0", return
5-39
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BTST -- Bit Test and Skip on True
BTST Examples: (Continued) 2. You can use BTST in the same way to manipulate a port pin address bit: BTST RET JP P2.0 LABEL3 ; If P2.0 = "1", then skip ; If P2.0 = "0", then return
3. Assume that P2.2, P2.3 and P3.0-P3.3 are cleared to "0": BP2 LD BTST RET INCS JR L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
L BP2
4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTST has the following effect: FLAG EQU * * * BITR * * LD BTST RET * * * 0A0H.0
EMB *
H,#0AH @H+FLAG
; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip
5-40
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BTSTZ -- Bit Test and Skip on True; Clear Bit
BTSTZ Operation: dst.b Operand mema.b memb.@L @H+DA.b Operation Summary Test specified bit; skip and clear if memory bit is set Bytes 2 2 2 Cycles 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is a "1", the instruction immediately following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is executed. The destination bit value is cleared. Operand mema.b * memb.@L 1 1 1 Binary Code 1 1 1 0 1 Operation Notation Skip if mema.b = 1 and clear
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
0 a3 0 a1
1 a2 1 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear Skip if [H + DA.3-0].b =1 and clear
@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. Port pin P2.0 is toggled by checking the P2.0 value (level): BTSTZ BITS JP P2.0 P2.0 LABEL3 ; If P2.0 = "1", then P2.0 "0" and skip ; If P2.0 = "0", then P2.0 "1"
2. Assume that port pins P2.2, P2.3 and P3.0-P3.3 are toggled: BP2 LD BTSTZ RET INCS JR L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
L BP2
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BTSTZ -- Bit Test and Skip on True; Clear Bit
BTSTZ Examples: (Continued) 3. Bank 0, location 0A0H.0, is tested and EMB = "0": FLAG EQU * * * BITR * * * LD BTSTZ BITS 0A0H.0
EMB
H,#0AH @H+FLAG @H+FLAG
; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip ; If 0A0H.0 = "0", then 0A0H.0 "1"
5-42
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
BXOR -- Bit Exclusive OR
BXOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Exclusive-OR carry with memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically XORed with the carry bit value. The resultant bit is written to the carry flag. The source value is unaffected. Operand C,mema.b * C,memb.@L 1 1 1 Binary Code 1 0 1 1 1 Operation Notation C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. The carry flag is logically XORed with the P1.0 value: RCF BXOR ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0"
C,P1.0
2. The P1 address is FF1H and register L contains the value 9H (1001B). The address (memb.7- 2) is 111100B and (L.3-2) = 10B. The resulting address is 11110010B or FF2H, specifying P2. The bit value for the BXOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P2.1: LD BXOR L,#9H C,P1.@L ; P1.@L is specified as P2.1; C XOR P2.1
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
BXOR -- Bit Exclusive OR
BXOR (Continued)
Examples:
3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BXOR EQU 20H.3 H,#2H C,@H+FLAG
; C XOR FLAG (20H.3)
5-44
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
CALL -- Call Procedure
CALL Operation: dst Operand ADR12 Operation Summary Call direct address(12 bits) Bytes 3 Cycles 4
Description:
CALL calls a subroutine located at the destination address. The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 14-Kbyte program memory address space. Operand ADR12 1 0 a7 1 1 a6 0 0 a5 Binary Code 1 1 0 1 a9 a1 1 a8 a0 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC11-8 SP SP - 6 PC11-0 ADR12
a12 a11 a10 a4 a3 a2
Example:
The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0E3FH. Executing the instruction CALL PLAY
at location 0123H will generate the following values: SP 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH PC = = = = = = = = 0FAH 0H EMB, ERB 2H 6H 0H 1H 0E3FH
Data is written to stack locations 0FFH-0FAH as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH 0 0 0 PC11 - PC8 0 0 0 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
5-45
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
CALLS -- Call Procedure (Short)
CALLS Operation: dst Operand ADR11 Operation Summary Call direct address within 2 K (11 bits) Bytes 2 Cycles 3
Description:
The CALLS instruction unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction. Then, it pushes the result onto the stack, decreasing the stack pointer six times. The higher bits of the PC, with the exception of the lower 11 bits, are cleared. The subroutine call must therefore be located within the 2-Kbyte block (0000H-07FFH) of program memory. Operand ADR11 1 1 1 Binary Code 0 1 a10 a9 a8 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC11-8 SP SP - 6 PC11 0 PC10-0 ADR11
a7
a6
a5
a4
a3
a2
a1
a0
Example:
The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0345H. Executing the instruction CALLS PLAY
at location 0123H will generate the following values: SP 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH PC = = = = = = = = 0FAH 0H EMB, ERB 2H 5H 0H 1H 0345H
Data is written to stack locations 0FFH-0FAH as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH 0 0 0 PC11 - PC8 0 0 0 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
5-46
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
CCF -- Complement Carry Flag
CCF Operation: Operand - Operation Summary Complement carry flag Bytes 1 Cycles 1
Description:
The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa. Operand - 1 1 0 Binary Code 1 0 1 1 0 CC Operation Notation
Example:
If the carry flag is logic zero, the instruction CCF changes the value to logic one.
5-47
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
COM -- Complement Accumulator
COM Operation: A A Operand Operation Summary Complement accumulator (A) Bytes 2 Cycles 2
Description:
The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice versa. Operand A 1 0 1 0 0 1 Binary Code 1 1 1 1 1 1 0 1 1 1 AA Operation Notation
Example:
If the accumulator contains the value 4H (0100B), the instruction COM A
leaves the value 0BH (1011B) in the accumulator.
5-48
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
CPSE -- Compare and Skip if Equal
CPSE Operation: dst,src Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR Operation Summary Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Bytes 2 2 2 1 2 2 Cycles 2+S 2+S 2+S 1+S 2+S 2+S
Description:
CPSE compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. Neither operand is affected by the comparison. Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR 1 d3 1 0 1 0 0 1 0 1 1 1 d2 1 1 1 1 0 1 0 1 1 0 d1 0 1 0 1 1 0 0 0 1 Binary Code 1 d0 1 1 1 0 1 1 0 1 0 1 0 1 d3 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 r1 0 d1 0 r1 0 0 0 0 r1 1 r0 1 d0 1 r0 0 0 1 0 0 Skip if EA = RR Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if A = R Skip if (HL) = im Operation Notation Skip if R = im
Example:
The extended accumulator contains the value 34H and register pair HL contains 56H. The second instruction (RET) in the instruction sequence CPSE RET EA,HL
is not skipped. That is, the subroutine returns since the result of the comparison is 'not equal.'
5-49
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
DECS -- Decrement and Skip on Borrow
DECS Operation: R RR dst Operand Operation Summary Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Bytes 1 2 Cycles 1+S 2+S
Description:
The destination is decremented by one. An original value of 00H will underflow to 0FFH. If a borrow occurs, a skip is executed. The carry flag value is unaffected. Operand R RR 0 1 1 1 1 1 0 0 0 Binary Code 0 1 1 1 1 1 r2 1 r2 r1 0 r1 r0 0 0 Operation Notation R R-1; skip on borrow RR RR-1; skip on borrow
Examples:
1. Register pair HL contains the value 7FH (01111111B). The following instruction leaves the value 7EH in register pair HL: DECS HL
2. Register A contains the value 0H. The following instruction sequence leaves the value 0FFH in register A. Since a "borrow" occurs, the 'CALL PLAY1' instruction is skipped and the 'CALL PLAY2' instruction is executed: DECS CALL CALL A PLAY1 PLAY2 ; "Borrow" occurs ; Skipped ; Executed
5-50
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
DI -- Disable Interrupts
DI Operation: Operand - Operation Summary Disable all interrupts Bytes 2 Cycles 2
Description:
Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts. Interrupts can still set their respective interrupt status latches, but the CPU will not directly service them. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 0 0 Operation Notation IME 0
Example:
If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction DI sets the IME bit to logic zero, disabling all interrupts.
5-51
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
EI -- Enable Interrupts
EI Operation: Operand - Operation Summary Enable all interrupts Bytes 2 Cycles 2
Description:
Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be serviced when they occur, assuming they are enabled. If an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 0 Operation Notation IME 1
Example:
If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction EI sets the IME bit to logic one, enabling all interrupts.
5-52
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
IDLE -- Idle Operation
IDLE Operation: Operand - Operation Summary Engage CPU idle mode Bytes 2 Cycles 2
Description:
IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (PCON). After an IDLE instruction has been executed, peripheral hardware remains operative. In application programs, an IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three NOP instructions are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus. Operand - 1 1 1 0 1 1 Binary Code 1 0 1 0 1 0 1 1 1 1 Operation Notation PCON.2 1
Example:
The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
5-53
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
INCS -- Increment and Skip on Carry
INCS Operation: R DA @HL RRb dst Operand Operation Summary Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 Cycles 1+S 2+S 2+S 1+S
Description:
The instruction INCS increments the value of the destination operand by one. An original value of 0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry flag value is unaffected. Operand R DA @HL RRb 0 1 a7 1 0 1 1 1 a6 1 1 0 0 0 a5 0 1 0 Binary Code 1 0 a4 1 0 0 1 1 a3 1 0 0 r2 0 a2 1 0 r2 r1 1 a1 0 1 r1 r0 0 a0 1 0 0 RRb RRb + 1; skip on carry (HL) (HL) + 1; skip on carry Operation Notation R R + 1; skip on carry DA DA + 1; skip on carry
Example:
Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The instruction sequence INCS INCS INCS @HL HL @HL ; 7EH "0" ; Skip ; 7EH "1"
leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a carry occurred, the second instruction is skipped. The carry flag value remains unchanged.
5-54
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
IRET -- Return From Interrupt
IRET Operation: Operand - Operation Summary Return from interrupt Bytes 1 Cycles 3
Description:
IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter. The stack pointer is incremented by six and the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically restored to their pre-interrupt values. Program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower-level or same-level interrupt was pending when the IRET was executed, IRET will be executed before the pending interrupt is processed. Operand - 1 1 0 Binary Code 1 0 1 0 1 Operation Notation PC11-8 (SP + 1) (SP) PC7-0 SP + 2) (SP + 3) PSW (SP + 4) (SP + 5) SP SP + 6
Example:
The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location 0122H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively. The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 123H. During a return from interrupt, data is popped from the stack to the program counter. The data in stack locations 0FFH-0FAH is organized as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH IS1 C 0 PC11 - PC8 0 0 0 PC3 - PC0 PC7 - PC4 IS0 SC2 EMB SC1 ERB SC0
5-55
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
JP -- Jump
JP Operation: dst Operand ADR12 Operation Summary Jump to direct address (12 bits) Bytes 3 Cycles 3
Description:
JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. The destination can be anywhere in the 4-Kbyte program memory address space. Operand ADR12 1 0 a7 1 0 a6 0 0 a5 Binary Code 1 0 a4 1 a3 0 a2 1 a9 a1 1 a8 a0 a11 a10 Operation Notation PC11-0 ADR12
Example:
The label 'SYSCON' is assigned to the instruction at program location 07FFH. The instruction JP SYSCON
at location 0123H will load the program counter with the value 07FFH.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
JPS -- Jump (Short)
JPS Operation: dst Operand ADR12 Operation Summary Jump direct in page (12 bits) Bytes 2 Cycles 2
Description:
JPS causes an unconditional branch to the indicated address with the 4-Kbyte program memory address space. Bits 0-11 of the program counter are replaced with the directly specified address. The destination address for this jump is specified to the assembler by a label or by an actual address in program memory. Operand ADR12 1 a7 0 a6 0 a5 Binary Code 1 a4 a11 a10 a3 a2 a9 a1 a8 a0 Operation Notation PC11-0 ADR12
Example:
The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction JPS SUB
at location 0EABH will load the program counter with the value 00FFH.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
JR -- Jump Relative (Very Short)
JR Operation: dst Operand #im @WX @EA Operation Summary Branch to relative immediate address Branch relative to contents of WX register Branch relative to contents of EA Bytes 1 2 2 Cycles 2 3 3
Description:
JR causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC. The range of the relative address is current PC - 15 to current PC + 16. The destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (-). For immediate addressing, the (+) range is from 2 to 16 and the (-) range is from -1 to -15. If a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. For JR @WX and JR @EA branch relative instructions, the valid range for the relative address is 0H-0FFH. The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. Normally, the 'JR @WX' and 'JR @EA' instructions jump to the address in the page in which the instruction is located. However, if the first byte of the instruction code is located at address 0xFEH or 0xFFH, the instruction will jump to the next page. Operand #im * @WX @EA 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 PC11-0 PC11-8 + (EA) Binary Code Operation Notation PC11-0 ADR (PC-15 to PC+16) PC11-0 PC11-8 + (WX)
First Byte
Condition a2 a2 a1 a1 a0 a0 PC PC+2 to PC+16 PC PC-1 to PC-15
* JR #im
0 0
0 0
0 0
1 0
a3 a3
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
JR -- Jump Relative (Very Short)
JR Examples: (Continued) 1. A short form for a relative jump to label 'KK' is the instruction JR KK where 'KK' must be within the allowed range of current PC-15 to current PC+16. The JR instruction has in this case the effect of an unconditional JP instruction. 2. In the following instruction sequence, if the instruction 'LD WX, #02H' were to be executed in place of 'LD WX,#00H', the program would jump to 0502H and 'JPS BBB' would be executed. If 'LD EA,#04H' were to be executed, the jump would be to 0504H and 'JPS CCC' would be executed. ORG JPS JPS JPS JPS LD LD ADS JR 0500H AAA BBB CCC DDD WX,#00H EA,WX WX,EA @WX ; WX 00H ; WX (WX) + (WX) ; Current PC11-8 (05H) + WX (00H) = 0500H ; Jump to address 0500H and execute JPS AAA
3. Here is another example: ORG LD LD LD LD LD JPS XXX LD JR 0600H A,#0H A,#1H A,#2H A,#3H 30H,A YYY EA,#00H @EA
; Address 30H A ; EA 00H ; Jump to address 0600H ; Address 30H 0H
If 'LD EA,#01H' were to be executed in place of 'LD EA,#00H', the program would jump to 0601H and address 30H would contain the value 1H. If 'LD EA,#02H' were to be executed, the jump would be to 0602H and address 30H would contain the value 2H.
5-59
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
LD -- Load
LD Operation: dst,src Operand A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA Operation Summary Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Bytes 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 Cycles 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2
Description:
The contents of the source are loaded into the destination. The source's contents are unaffected. If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two times in succession, only the first LD will be executed; the other similar instructions that immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect' (see examples below). Operand A,#im A,@RRa A,DA A,Ra Ra,#im 1 1 1 a7 1 0 1 d3 0 0 0 a6 1 0 1 d2 1 0 0 a5 0 0 0 d1 Binary Code 1 0 0 a4 1 0 1 d0 d3 1 1 a3 1 1 1 1 d2 i2 1 a2 1 r2 0 r2 d1 i1 0 a1 0 r1 0 r1 d0 i0 0 a0 1 r0 1 r0 Ra im A Ra A im A (RRa) A DA Operation Notation
5-60
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
LD -- Load
LD Description: (Continued) Operand RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA 1 d7 1 a7 1 0 1 0 1 a7 1 1 1 1 a7
1 1
Binary Code 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6
1 1
Operation Notation r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2
1 r2
0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5
0 1
0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4
1 1
0 d3 1 a3 1 0 1 1 1 a3 1 1 0 1 a3
1 0
r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1
0 r1
1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0
0 0
RR imm DA A Ra A A (HL), E (HL + 1) A DA, E DA + 1 EA RRb (HL) A DA A, DA + 1 E RRb EA (HL) A, (HL + 1) E
1 0
1 0
0 0
1 0
1 0
1 0
0 0
0 0
Examples:
1. RAM location 30H contains the value 4H. The RAM location values are 40H, 41H, and 0AH, 3H respectively. The following instruction sequence leaves the value 40H in point pair HL, 0AH in the accumulator and in RAM location 40H, and 3H in register E. LD LD LD LD LD HL,#30H A,@HL HL,#40H EA,@HL @HL,A ; ; ; ; ; HL 30H A 4H HL 40H A 0AH, E 3H RAM (40H) 0AH
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
LD -- Load
LD Examples: (Continued) 2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two times in succession, only the first LD is executed; the next instructions are treated as NOPs. Here are two examples of this 'redundancy effect': LD LD LD LD LD LD LD LD LD A,#1H EA,#2H A,#3H 23H,A HL,#10H HL,#20H A,#3H EA,#35 @HL,A ; ; ; ; ; ; ; ; ; A 1H NOP NOP (23H) 1H HL 10H NOP A 3H NOP (10H) 3H
The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes: Instruction LD A,#im Operation Description and Guidelines Since the 'redundancy effect' occurs with instructions like LD EA,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like NOPs. Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX, WL) to the A register. Load direct data memory contents to the A register. Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register. Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z).
LD A,@RRa
LD A,DA LD A,Ra LD Ra,#im
LD RR,#imm Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a redundancy effect if the operation addresses the HL or EA registers. LD DA,A LD Ra,A Load contents of register A to direct data memory address. Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y).
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
LD -- Load
LD Examples: (Concluded) Instruction LD EA,@HL Operation Description and Guidelines Load data memory contents pointed to by 8-bit register HL to the A register, and the contents of HL+1 to the E register. The contents of register L must be an even number. If the number is odd, the LSB of register L is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to HL and the next instruction 'LD EA,@HL' loads the contents of 36H to register A and the contents of 37H to register E. Load direct data memory contents of DA to the A register, and the next direct data memory contents of DA + 1 to the E register. The DA value must be an even number. If it is an odd number, the LSB of DA is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD EA,37H' loads the contents of 36H to the A register and the contents of 37H to the E register. Load 8-bit RRb register (HL, WX, YZ) to the EA register. H, W, and Y register values are loaded into the E register, and the L, X, and Z values into the A register. Load A register contents to data memory location pointed to by the 8-bit HL register value. Load the A register contents to direct data memory and the E register contents to the next direct data memory location. The DA value must be an even number. If it is an odd number, the LSB of the DA value is recognized as logic zero (an even number), and is not replaced with the true value. Load contents of EA to the 8-bit RRb register (HL, WX, YZ). The E register is loaded into the H, W, and Y register and the A register into the L, X, and Z register. Load the A register to data memory location pointed to by the 8-bit HL register, and the E register contents to the next location, HL + 1. The contents of the L register must be an even number. If the number is odd, the LSB of the L register is recognized as logic zero (an even number), and is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to register HL; the instruction 'LD @HL,EA' loads the contents of A into address 36H and the contents of E into address 37H.
LD EA,DA
LD EA,RRb
LD @HL,A
LD DA,EA
LD RRb,EA
LD @HL,EA
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
LDB -- Load Bit
LDB LDB Operation: dst,src.b dst.b,src Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load memory bit to a specified carry bit Load indirect memory bit to a specified carry bit Operation Summary Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Bytes 2 2 2 2 2 2 Cycles 2 2 2 2 2 2
Description:
The Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. One of the operands must be the carry flag; the other may be any directly or indirectly addressable bit. The source is unaffected. Operand mema.b,C * memb.@L,C @H+DA.b,C C,mema.b* C,memb.@L C,@H+DA.b 1 1 1 Binary Code 1 1 1 0 0 Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H + [DA.3-0].b (C) C mema.b C memb.7-2 + [L.3-2] . [L.1-0] C [H + DA.3-0].b
1 0 1 0 1 1 0 1 0
1 1 1 b2 1 1 1 1 b2
1 0 1 b1 1 1 0 1 b1
1 0 1 b0 1 1 0 1 b0
1 a5 1 a3 0 0 a5 0 a3
1 a4 1 a2 1 1 a4 1 a2
0 a3 0 a1 0 0 a3 0 a1
0 a2 0 a0 0 0 a2 0 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF1H-FF9H
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
LDB -- Load Bit
LDB Examples: (Continued) 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. LDB C,P1.0
2. The P1 address is FF1H and the L register contains the value 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) is 10B. The resulting address is 11110010B or FF2H and P2 is addressed. The bit value (L.1-0) is specified as 01B (bit 1). LD LDB L,#9H C,P1.@L ; P1.@L specifies P2.1 and C P2.1
3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is 3. Therefore, @H+FLAG = 20H.3. FLAG LD LDB EQU 20H.3 H,#2H C,@H+FLAG
; C FLAG (20H.3)
4. The following instruction sequence sets the carry flag and the loads the "1" data value to the output pin P2.0, setting it to output mode: SCF LDB ; C "1" ; P2.0 "1"
P2.0,C
5. The P1 address is FF1H and L = 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) is 10B. The resulting address, 11110010B specifies P2. The bit value (L.1-0) is specified as 01B (bit 1). Therefore, P1.@L = P2.1. SCF LD LDB ; C "1" L,#9H P1.@L,C ; P1.@L specifies P2.1 ; P2.1 "1"
6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit value is 3, @H+FLAG = 20H.3: FLAG RCF LD LDB EQU 20H.3 H,#2H @H+FLAG,C ; C "0" ; FLAG(20H.3) "0"
NOTE: Port pin names used in examples 4 and 5 may vary with different SAM47 devices.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
LDC -- Load Code Byte
LDC Operation: dst,src Operand EA,@WX EA,@EA Operation Summary Load code byte from WX to EA Load code byte from EA to EA Bytes 1 1 Cycles 3 3
Description:
This instruction is used to load a byte from program memory into an extended accumulator. The address of the byte fetched is the five highest bit values in the program counter and the contents of an 8-bit working register (either WX or EA). The contents of the source are unaffected. Operand EA,@WX EA,@EA 1 1 1 1 0 0 Binary Code 0 0 1 1 1 0 0 0 0 0 Operation Notation EA [PC11-8 + (WX)] EA [PC11-8 + (EA)]
Examples:
1. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: LD CALL JPS ORG DB DB DB DB * * * DISPLAY RET 66H 77H 88H 99H EA,#00H DISPLAY MAIN 0500H
LDC
EA,@EA
; EA address 0500H = 66H
If the instruction 'LD EA,#01H' is executed in place of 'LD EA,#00H', The content of 0501H (77H) is loaded to the EA register. If 'LD EA,#02H' is executed, the content of address 0502H (88H) is loaded to EA.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
LDC -- Load Code Byte
LDC Examples: (Continued) 2. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: ORG DB DB DB DB * * * DISPLAY LD LDC RET 0500 66H 77H 88H 99H
WX,#00H EA,@WX
; EA address 0500H = 66H
If the instruction 'LD WX,#01H' is executed in place of 'LD WX,#00H', then EA address 0501H = 77H. If the instruction 'LD WX,#02H' is executed in place of 'LD WX,#00H', then EA address 0502H = 88H. 3. Normally, the LDC EA, @EA and the LDC EA, @WX instructions reference the table data on the page on which the instruction is located. If, however, the instruction is located at address xxFFH, it will reference table data on the next page. In this example, the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A: ORG 01FDH 01FFH 01FDH LD LDC WX,#00H EA,@WX ; ; E upper 4 bits of 0200H address A lower 4 bits of 0200H address
4. Here is another example of page referencing with the LDC instruction: ORG 0100
DB 67H SMB 0 LD HL,#30H ; LD WX,#00H LDC EA,@WX ; LD @HL,EA ;
Even number E upper 4 bits of 0100H address ; A lower 4 bits of 0100H address RAM (30H) 7, RAM (31H) 6
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
LDD -- Load Data Memory and Decrement
LDD Operation: dst Operand A,@HL Operation Summary Load indirect data memory contents to A; decrement register L contents and skip on borrow Bytes 1 Cycles 2+S
Description:
The contents of a data memory location are loaded into the accumulator, and the contents of the register L are decreased by one. If a "borrow" occurs (e.g., if the resulting value in register L is 0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH
Example:
In this example, assume that register pair HL contains 20H and internal RAM location 20H contains the value 0FH: LD LDD JPS JPS HL,#20H A,@HL XXX YYY ; A (HL) and L L-1 ; Skip ; H 2H and L 0FH
The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and instruction 'JPS YYY' is executed.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
LDI -- Load Data Memory and Increment
LDI Operation: dst,src Operand A,@HL Operation Summary Load indirect data memory to A; increment register L contents and skip on overflow Bytes 1 Cycles 2+S
Description:
The contents of a data memory location are loaded into the accumulator, and the contents of the register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is 0H), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H
Example:
Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value 0FH: LD LDI JPS JPS HL,#2FH A,@HL XXX YYY ; A (HL) and L L+1 ; Skip ; H 2H and L 0H
The instruction 'JPS XXX' is skipped since an overflow occurred after the 'LDI A,@HL' and the instruction 'JPS YYY' is executed.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
NOP -- No Operation
NOP Operation: Operand - No operation Operation Summary Bytes 1 Cycles 1
Description:
No operation is performed by a NOP instruction. It is typically used for timing delays. One NOP causes a 1-cycle delay: with a 1 s cycle time, five NOPs would therefore cause a 5 s delay. Program execution continues with the instruction immediately following the NOP. Only the PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction. Operand - 1 0 1 Binary Code 0 0 0 0 0 Operation Notation No operation
Example:
Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power-down mode is initiated: STOP NOP NOP NOP
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
OR -- Logical OR
OR Operation: dst,src Operand A, #im A, @HL EA,RR RRb,EA Operation Summary Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
The source operand is logically ORed with the destination operand. The result is stored in the destination. The contents of the source are unaffected. Operand A, #im A, @HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 0 1 1 0 1 0 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 0 0 0 0 0 RRb RRb OR EA A A OR (HL) EA EA OR RR Operation Notation A A OR im
Example:
If the accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction OR EA,@HL
leaves the value 0D7H (11010111B) in the accumulator .
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
POP -- Pop From Stack
POP Operation: dst Operand RR SB Operation Summary Pop to register pair from stack Pop SMB and SRB values from stack Bytes 1 2 Cycles 1 2
Description:
The contents of the RAM location addressed by the stack pointer is read, and the SP is incremented by two. The value read is then transferred to the variable indicated by the destination operand. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 0 1 0 Operation Notation RRL (SP), RRH (SP+1) SP SP+2 (SRB) (SP), SMB (SP+1), SP SP+2
Example:
The SP value is equal to 0EDH, and RAM locations 0EFH through 0EDH contain the values 2H, 3H, and 4H, respectively. The instruction POP HL
leaves the stack pointer set to 0EFH and the data pointer pair HL set to 34H.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
PUSH -- Push Onto Stack
PUSH Operation: src Operand RR SB Operation Summary Push register pair onto stack Push SMB and SRB values onto stack Bytes 1 2 Cycles 1 2
Description:
The SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer, thereby adding a new element to the top of the stack. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 1 1 1 Operation Notation (SP-1) RRH, (SP-2) RRL SP SP-2 (SP-1) SMB, (SP-2) SRB; (SP) SP-2
Example:
As an interrupt service routine begins, the stack pointer contains the value 0FAH and the data pointer register pair HL contains the value 20H. The instruction PUSH HL
leaves the stack pointer set to 0F8H and stores the values 2H and 0H in RAM locations 0F9H and 0F8H, respectively.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
RCF -- Reset Carry Flag
RCF Operation: Operand - Operation Summary Reset carry flag to logic zero Bytes 1 Cycles 1
Description:
The carry flag is cleared to logic zero, regardless of its previous value. Operand - 1 1 1 Binary Code 0 0 1 1 0 C0 Operation Notation
Example:
Assuming the carry flag is set to logic one, the instruction RCF resets (clears) the carry flag to logic zero.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
REF -- Reference Instruction
REF Operation: dst Operand memc Reference code Operation Summary Bytes 1 Cycles 3*
*
Description:
The REF instruction for a 16K CALL instruction is 4 cycles.
The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the REF instruction reference area in program memory. REF reduces the number of program memory accesses for a program. Operand memc t7 t6 t5 Binary Code t4 t3 t2 t1 t0 Operation Notation PC11-0 = memc7-4, memc3-0 < 1
TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area: 1. When the reference area is specified by the TJP instruction, memc.7-6 = 00 PC11-0 memc.3-0 + (memc + 1) 2. When the reference area is specified by the TCALL instruction, memc.7-6 = 01 (SP-4) (SP-1) (SP-2) PC11-0 SP-3 EMB, ERB, 0, 0 PC11-0 memc.3-0 + (memc + 1) SP SP-4 When the reference area is specified by any other instruction, the 'memc' and 'memc + 1' instructions are executed. Instructions referenced by REF occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In addition, the destination address of the TJP and TCALL instructions must be located with the 0FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS. If the instruction following a REF is subject to the 'redundancy effect', the redundant instruction is skipped. If, however, the REF follows a redundant instruction, it is executed. On the other hand, the binary code of a REF instruction is 1 byte. The upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction ( x 1/2) becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below).
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
REF -- Reference Instruction
REF Examples: (Continued) 1. Instructions can be executed efficiently using REF, as shown in the following example: ORG AAA BBB CCC DDD 0020H LD LD TCALL TJP * * * ORG REF REF REF REF AAA BBB CCC DDD HL,#00H EA,#FFH SUB1 SUB2
0080H ; ; ; ; LD LD CALL JP HL,#00H EA,#FFH SUB1 SUB2
2. The following example shows how the REF instruction is executed in relation to LD instructions that have a 'redundancy effect': ORG AAA 0020H LD * * * ORG LD REF * * REF LD SRB EA,#30H AAA EA,#40H
0100H ; Not skipped
AAA EA,#50H 2
; Skipped
5-76
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
REF -- Reference Instruction
REF Examples: (Concluded) 3. In this example the binary code of 'REF A1' at locations 20H-21H is 20H, for 'REF A2' at locations 22H-23H, it is 21H, and for 'REF A3' at 24H-25H, the binary code is 22H :
Opcode
Symbol
Instruction ORG 0020H LD LD LD LD LD LD LD LD LD TCALL TJP * * * ORG A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2
83 83 83 83 83 83 83 83 83 41 01
00 03 05 10 26 08 0F F0 67 0B 0D
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
0100H ; ; ; ; ; ; ; ; ; ; ; LD LD LD LD LD LD LD LD LD CALL JP HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2
20 21 22 23 24 25 26 27 30 31 32
REF REF REF REF REF REF REF REF REF REF REF
5-77
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
RET -- Return From Subroutine
RET Operation: Operand - Operation Summary Return from subroutine Bytes 1 Cycles 3
Description:
RET pops the PC values successively from the stack, incrementing the stack pointer by six. Program execution continues from the resulting address, generally the instruction immediately following a CALL or CALLS. Operand - 1 1 0 Binary Code 0 0 1 0 1 Operation Notation PC11-8 (SP+1) (SP) PC7-0 (SP+2) (SP+3) PSW EMB,ERB SP SP+ 6
Example:
The stack pointer contains the value 0FAH. RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain 1H, 0H, 5H, and 2H, respectively. The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H. During a return from subroutine, PC values are popped from stack locations as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0 PC11 - PC8 0 0 0 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
5-78
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
RRC -- Rotate Accumulator Right Through Carry
RRC Operation: A Operand A Operation Summary Rotate right through carry bit Bytes 1 Cycles 1
Description:
The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position.
3 C 0
Operand A 1 0 0
Binary Code 0 1 0 0 0
Operation Notation C A.0, A3 C A.n-1 A.n (n = 1, 2, 3)
Example:
The accumulator contains the value 5H (0101B) and the carry flag is cleared to logic zero. The instruction RRC A
leaves the accumulator with the value 2H (0010B) and the carry flag set to logic one.
5-79
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
SBC -- Subtract With Carry
SBC Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2
Description:
SBC subtracts the source and carry flag value from the destination operand, leaving the result in the destination. SBC sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. The contents of the source are unaffected. If the carry flag was set before the SBC instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. In this case, the carry bit is subtracted from the destination along with the source operand. Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 0 0 0 0 0 C,RRb RRb - EA - C Operation Notation C,A A - (HL) - C C, EA EA -RR - C
Examples:
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF SBC JPS ; C "1" ; EA 0C3H - 0AAH - 1H, C "0" ; Jump to XXX; no skip after SBC
EA,HL XXX
2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF SBC JPS ; C "0" ; EA 0C3H - 0AAH - 0H = 19H, C "0" ; Jump to XXX; no skip after SBC
EA,HL XXX
5-80
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
SBC -- Subtract With Carry
SBC Examples: (Continued) 3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on 'no borrow' to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'SBC A,@HL' instruction does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. a. 8 - 6 decimal addition (the contents of the address specified by the HL register is 6H): RCF LD SBC ADS JPS ; ; ; ; C "0" A 8H A 8H - 6H - C(0) = 2H, C "0" Skip this instruction because no borrow after SBC result
A,#8H A,@HL A,#0AH XXX
b. 3 - 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD SBC ADS ; ; ; ; ; ; C "0" A 3H A 3H - 4H - C(0) = 0FH, C "1" No skip. A 0FH + 0AH = 9H (The skip function of 'ADS A,#im' is inhibited after a 'SBC A,@HL' instruction even if an overflow occurs.)
A,#3H A,@HL A,#0AH
JPS
XXX
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
SBS -- Subtract
SBS Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Bytes 1 2 2 Cycles 1+S 2+S 2+S
Description:
The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. A skip is executed if a borrow occurs. The value of the carry flag is not affected. Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 1 0 0 0 0 RRb RRb - EA; skip on borrow Operation Notation A A - (HL); skip on borrow EA EA - RR; skip on borrow
Examples:
1. The accumulator contains the value 0C3H, register pair HL contains the value 0C7H, and the carry flag is cleared to logic zero: RCF SBS ; ; ; ; ; ; C "0" EA 0C3H - 0C7H, C "0" SBS instruction skips on borrow, but carry flag value is not affected Skip because a borrow occurred Jump to YYY is executed
EA,HL
JPS JPS
XXX YYY
2. The accumulator contains the value 0AFH, register pair HL contains the value 0AAH, and the carry flag is set to logic one: SCF SBS JPS ; ; ; ; C "1" EA 0AFH - 0AAH, C "1" Jump to XXX JPS was not skipped since no "borrow" occurred after SBS
EA,HL XXX
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
SCF -- Set Carry Flag
SCF Operation: Operand - Operation Summary Set carry flag to logic one Bytes 1 Cycles 1
Description:
The SCF instruction sets the carry flag to logic one, regardless of its previous value. Operand - 1 1 1 Binary Code 0 0 1 1 1 C1 Operation Notation
Example:
If the carry flag is cleared to logic zero, the instruction SCF sets the carry flag to logic one.
5-83
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
SMB -- Select Memory Bank
SMB Operation: n Operand n Operation Summary Select memory bank Bytes 2 Cycles 2
Description:
The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. The constants 0, 1, and 15 are usually used as the SMB operand to select the corresponding memory bank. All references to data memory addresses fall within the following address ranges: Please note that since data memory spaces differ for various devices in the SAM47 product family, the 'n' value of the SMB instruction will also vary. Addresses 000H-01FH 020H-0FFH 1E0H-1FFH F80H-FFFH Register Areas Working registers Stack and general-purpose registers Display registers I/O-mapped hardware registers 1 15 1 15 Bank 0 SMB 0
The enable memory bank (EMB) flag must always be set to "1" in order for the SMB instruction to execute successfully for memory banks 0, 1, and 15. Format n 1 0 1 1 0 0 Binary Code 1 0 1 d3 1 d2 0 d1 1 d0 Operation Notation SMB n (n = 0, 1, 15)
Example:
If the EMB flag is set, the instruction SMB 0
selects the data memory address range for bank 0 (000H-0FFH) as the working memory bank.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
SRB -- Select Register Bank
SRB Operation: n Operand n Operation Summary Select register bank Bytes 2 Cycles 2
Description:
The SRB instruction selects one of four register banks in the working register memory area. The constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB settings: ERB Setting 3 0 1 0 0 SRB Settings 2 0 0 1 x 0 0 1 1
NOTE: 'x' = not applicable.
Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3
The enable register bank flag (ERB) must always be set for the SRB instruction to execute successfully for register banks 0, 1, 2, and 3. In addition, if the ERB value is logic zero, register bank 0 is always selected, regardless of the SRB value. Operand n 1 0 1 1 0 0 Binary Code 1 1 1 0 1 0 0 d1 1 d0 Operation Notation SRB n (n = 0, 1, 2, 3)
Example:
If the ERB flag is set, the instruction SRB 3
selects register bank 3 (018H-01FH) as the working memory register bank.
5-85
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
SRET -- Return From Subroutine and Skip
SRET Operation: Operand - Operation Summary Return from subroutine and skip Bytes 1 Cycles 3+S
Description:
SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL or CALLS instruction. SRET skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. Then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. Operand - 1 1 1 Binary Code 0 0 1 0 1 Operation Notation PC11-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 5) (SP + 4) SP SP + 6 then skip
Example:
If the stack pointer contains the value 0FAH and RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain the values 1H, 0H, 5H, and 2H, respectively, the instruction SRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0125H. then skips unconditionally. During a return from subroutine, data is popped from the stack to the PC as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0 PC11 - PC8 0 0 0 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
5-86
KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
STOP -- Stop Operation
STOP Operation: Operand - Operation Summary Engage CPU stop mode Bytes 2 Cycles 2
Description:
The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one. When STOP executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 1 Operation Notation PCON.3 1
Example:
Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception of some peripheral hardware). The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
VENT -- Load EMB, ERB, and Vector Address
VENTn Operation: dst Operand EMB (0,1) ERB (0,1) ADR Operation Summary Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location. Bytes 2 Cycles 2
Description:
The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to the corresponding branching locations. The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. After the return from interrupt (IRET) you do not need to set the EMB and ERB values again. Instead, use BITR and BITS to clear these values in your program routine. The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction. These addresses must be stored in ROM locations 0000H-0FFFH. Generally, the VENTn instructions are coded starting at location 0000H. The format for VENT instructions is as follows: VENTn d1,d2,ADDR
EMB d1 ("0" or "1") ERB d2 ("0" or "1") PC ADDR (address to branch n = device-specific module address code (n = 0-n) Operand EMB (0,1) ERB (0,1) ADR E M B E R B 0 Binary Code 0 a11 a10 a9 a8 Operation Notation ROM (2 x n) 7-6 EMB, ERB ROM (2 x n) 5-4 0, PC12 ROM (2 x n) 3-0 PC11-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7)
a7
a6
a5
a4
a3
a2
a1
a0
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
VENT -- Load EMB, ERB, and Vector Address
VENTn Example: (Continued) The instruction sequence ORG VENT0 VENT1 VENT2 VENT3 ORG VENT5 0000H 1,0,RESET 0,1,INTB 0,1,INT0 0,1,INT1 000AH 0,1,INTT0
causes the program sequence to branch to the RESET routine labeled 'RESET,' setting EMB to "1" and ERB to "0" when RESET is activated. When a basic timer interrupt is generated, VENT1 causes the program to branch to the basic timer's interrupt service routine, INTB, and to set the EMB value to "0" and the ERB value to "1". VENT2 then branches to INT0, VENT3 to INT1, and so on, setting the appropriate EMB and ERB values.
5-89
SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
XCH -- Exchange A or EA with Nibble or Byte
XCH Operation: dst,src Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL Operation Summary Exchange A and data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Bytes 2 1 1 2 2 2 Cycles 2 1 1 2 2 2
Description:
The instruction XCH loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL 0 a7 0 0 1 a7 1 1 1 0 1 a6 1 1 1 a6 1 1 1 0 1 a5 1 1 0 a5 0 1 0 0 Binary Code 1 a4 0 1 0 a4 1 0 1 0 1 a3 1 1 1 a3 1 0 1 0 0 a2 r2 i2 1 a2 1 r2 1 0 0 a1 r1 i1 1 a1 0 r1 0 0 1 a0 r0 i0 1 a0 0 0 0 1 A (HL), E (HL + 1) EA RRb A Ra A (RRa) A DA,E DA + 1 Operation Notation A DA
Example:
Double register HL contains the address 20H. The accumulator contains the value 3FH (00111111B) and internal RAM location 20H the value 75H (01110101B). The instruction XCH EA,@HL
leaves RAM location 20H with the value 3FH (00111111B) and the extended accumulator with the value 75H (01110101B).
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
XCHD -- Exchange and Decrement
XCHD Operation: dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; decrement contents of register L and skip on borrow Bytes 1 Cycles 2+S
Description:
The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L. If the content of register L is 0FH, the next instruction is skipped. The value of the carry flag is not affected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH
Example:
Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH: LD LD XCHD JPS JPS YYY HL,#20H A,#0H A,@HL XXX YYY
; A 0FH and L L - 1, (HL) "0" ; Skipped since a borrow occurred ; H 2H, L 0FH ; (2FH) 0FH, A (2FH), L L - 1 = 0EH
XCHD A,@HL * * *
The 'JPS YYY' instruction is executed since a skip occurs after the XCHD instruction.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
XCHI -- Exchange and Increment
XCHI Operation: dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; increment contents of register L and skip on overflow Bytes 1 Cycles 2+S
Description:
The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L. If the content of register L is 0H, a skip is executed. The value of the carry flag is not affected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H
Example:
Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH: LD LD XCHI JPS JPS YYY XCHI * * * HL,#2FH A,#0H A,@HL XXX YYY A,@HL
; A 0FH and L L + 1 = 0, (HL) "0" ; Skipped since an overflow occurred ; H 2H, L 0H ; (20H) 0FH, A (20H), L L + 1 = 1H
The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction.
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KS57C2302/C2304/P2304 MICROCONTROLLER
SAM47 INSTRUCTION SET
XOR -- Logical Exclusive OR
XOR Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
XOR performs a bit wise logical XOR operation between the source and destination variables and stores the result in the destination. The source contents are unaffected. Operand A,#im A,@HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 0 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb XOR EA A A XOR (HL) EA EA XOR (RR) Operation Notation A A XOR im
Example:
If the extended accumulator contains 0C3H (11000011B) and register pair HL contains 55H (01010101B), the instruction XOR EA,HL
leaves the value 96H (10010110B) in the extended accumulator.
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SAM47 INSTRUCTION SET
KS57C2302/C2304/P2304 MICROCONTROLLER
NOTES
5-94
Oscillator Circuits Interrupts Power-Down
RESET
I/O Ports Timers and Timer/Counters LCD Controller/Driver Electrical Data Mechanical Data KS57P2304 OTP Development Tools
KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
6
OVERVIEW -- Basic timer
OSCILLATOR CIRCUITS
The KS57C2302/C2304microcontroller has two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. Specifically, a clock pulse is required by the following peripheral modules: -- LCD controller -- Timer/counter 0 -- Watch timer -- Clock output circuit CPU Clock Notation In this document, the following notation is used for descriptions of the CPU clock: fx Main system clock fxt Subsystem clock fxx Selected system clock
6-1
OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
Clock Control Registers When the system clock mode control register, SCMOD, and the power control register, PCON, are both cleared to zero after RESET, the normal CPU operating mode is enabled, a main system clock of fx/64 is selected, and main system clock oscillation is initiated. PCON is used to select normal CPU operating mode or one of two power-down modes -- stop or idle. Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power-down mode. The system clock mode control register, SCMOD, lets you select the main system clock (fx) or a subsystem clock (fxt) as the CPU clock and to start (or stop) main or sub system clock oscillation. The resulting clock source, either main system clock or subsystem clock, is referred to as the CPU clock. The main system clock is selected and oscillation started when all SCMOD bits are cleared to logic zero. By setting SCMOD.3-.2 and SCMOD.0 to different values, CPU can operate in a subsystem clock source and start or stop main or sub system clock oscillation. To stop main system clock oscillation, you must use the STOP instruction (assuming the main system clock is selected) or manipulate SCMOD.3 to "1" (assuming the sub system clock is selected). The main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be divided by 4. By manipulating PCON bits 1 and 0, you select one of the following frequencies as CPU clock. fx/4, fxt/4, fx/8, fx/64 Using a Subsystem Clock If a subsystem clock is being used as the selected system clock, the idle power-down mode can be initiated by executing an IDLE instruction. The subsystem clock can be stopped by setting SCMOD.2 to "1". The watch timer, buzzer and LCD display operate normally with a subsystem clock source, since they operate at very slow speeds (122 s at 32.768 kHz) and with very low power consumption.
6-2
KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
Main-system Oscillator Circuit
fx
fxt
Subsystem Oscillator
Watch Timer LCD Controller
Selector
Xin Xout
OSC Stop fxx 1/8 - 1/4096
XTin
XTout
Oscillator stop
Frequenc y Dividing
1/2
1/16
Basic Timer Timer/Counter Watch Timer LCD Controller Clock Output Circuit
SCMOD.3 Selector SCMOD.0
fx/1,2,16
SCMOD.2
fxt
Selector
1/4
PCON.0 PCON.1
CPU clock
CPU stop signal (By IDLE or STOP instruction)
IDLE STOP
PCON.2 PCON.3 Oscillator Control Circuit
Wait release signal Internal RESET signal
Power down release
Clear
PCON.3, .2 fx : Main-system clock fxt : Sub-system clock fxx : System clock
Figure 6-1. Clock Circuit Diagram
6-3
OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
MAIN SYSTEM OSCILLATOR CIRCUITS
SUBSYSTEM OSCILLATOR CIRCUITS
Xin
XTin
Xout
32.768 kHz
XTout
Figure 6-2. Crystal/Ceramic Oscillator
Figure 6-5. Crystal/Ceramic Oscillator
Xin
EXTERNAL CLOCK
XTin
Xout
XTout
Figure 6-3. External Oscillator
Figure 6-6. External Oscillator
Xin R Xout
Figure 6-4. RC Oscillator
6-4
KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
POWER CONTROL REGISTER (PCON) The power control register (PCON) is a 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. The PCON can be addressed directly by 4-bit write instructions or indirectly by the instructions IDLE and STOP. FB3H PCON.3 PCON.2 PCON.1 PCON.0 PCON
PCON.3 and PCON.2 can be addressed only by the STOP and IDLE instructions, respectively, to engage the idle and stop power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (EMB). PCON bits 1 and 0 can be written only by 4-bit RAM control instruction. PCON is a write-only register. There are three basic choices: -- Main system clock (fx) or subsystem clock (fxt); -- Divided fx clock frequency of 4, 8, or 64 -- Divided fxt clock frequency of 4. PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If SCMOD.0 = "0", the main system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 = "1" the subsystem clock is selected. RESET sets PCON register values (and SCMOD) to logic zero. Table 6-1. Power Control Register (PCON) Organization PCON Bit Settings PCON.1 0 1 1 PCON.0 0 0 1 Resulting CPU Clock Frequency SCMOD.0 = 0 fx/64 fx/8 fx/4 Resulting CPU Operating Mode Normal CPU operating mode IDLE STOP mode SCMOD.0 = 1 fxt/4
PCON Bit Settings PCON.3 0 0 1 PCON.2 0 1 0
6-5
OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Setting the CPU Clock
To set the CPU clock to 0.95 s at 4.19 MHz: BITS SMB LD LD EMB 15 A,#3H PCON,A
INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds. Table 6-2. Instruction Cycle Times for CPU Clock Rates Oscillation Source fx = 4.19 MHz Selected CPU Clock fx/64 fx/8 fx/4 fxt = 32.768 kHz fxt/4 Resulting Frequency 65.5 kHz 524.0 kHz 1.05 MHz 8.19 kHz Cycle Time (sec) 15.3 1.91 0.95 122.0
6-6
KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
SYSTEM CLOCK MODE REGISTER (SCMOD) The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control main and sub-system clock oscillation. SCMOD is mapped to the RAM address FB7H. When main system clock is used as clock source, main system clock oscillation can be stopped by STOP instruction or setting SCMOD.3 (not recommended). When the clock source is subsystem clock, main system clock oscillation is stopped by setting SCMOD.3. SCMOD.0, SCMOD2 and SCMOD.3 cannot be simultaneously modified. Sub-oscillation goes into stop mode only by SCMOD.2. PCON which revokes stop mode cannot stop the sub-oscillation. The stop of sub-oscillation is released only by reset.
RESET clears all SCMOD values to logic zero, selecting the main system clock (fx) as the CPU clock and starting clock oscillation. The reset value of the SCMOD is 0.
SCMOD.3, SCMOD.2, SCMOD.0 bits can be manipulated by 1-bit write instructions (In other words, SCMOD.0, SCMOD.2 and SCMOD.3 cannot be modified simultaneously by a 4-bit write). Bit 1 is always logic zero. FB7H SCMOD.3 SCMOD.2 "0" SCMOD.0 SCMOD
A subsystem clock (fxt) can be selected as the system clock by manipulating the SCMOD.3 and SCMOD.0 bit settings. If SCMOD.3 = "0" and SCMOD.0 = "1", the subsystem clock is selected and main system clock oscillation continues. If SCMOD.3 = "1" and SCMOD.0 = "1", fxt is selected, but main system clock oscillation stops. If you have selected fx as the CPU clock, setting SCMOD.3 to "1" will stop main system clock oscillation. But this mode must not be used. To stop main system clock oscillation safely, main oscillation clock should be stopped only by a STOP instruction in main system clock mode. Table 6-3. System Clock Mode Register (SCMOD) Organization SCMOD Register Bit Settings SCMOD.3 0 0 0 1 SCMOD.2 0 1 0 0 SCMOD.0 0 0 1 1 Resulting Clock Selection fx Oscillation On On On Off fxt Oscillation On Off On On CPU Clock (note) fx fx fxt fxt
NOTE: CPU clock is selected by PCON register settings.
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OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 6-4. Main/Sub Oscillation Stop Mode Mode Main Oscillation STOP Mode Condition Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Method to issue Osc Stop STOP instruction: Main oscillator stops. CPU is in idle mode. Sub oscillator still runs (stops). Osc Stop Release Source (2) Interrupt and reset: After releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. And then the CPU operates. Oscillation stabilization time is 1/ {256 x BT clock (fx)}. Reset: Interrupt can't start the main oscillation. Therefore, the CPU operation can never be restarted. BToverflow and reset: After the overflow of basic timer [1/ {256 x BT clock (fxt)}], CPU operation and main oscillation automatically start. Set SCMOD.3 to "0" or reset
Set SCMOD.3 to "1" (1) Main oscillator stops, halting the CPU operation. Sub oscillator still runs (stops). Main oscillator runs. Sub oscillator runs. System clock is the sub oscillation clock. STOP instruction: (1) Main oscillator stops. CPU is in idle mode. Sub oscillator still runs. Set SCMOD.3 to "1" Main oscillator stops. CPU still operates. Sub oscillator still runs. Sub oscillation STOP Mode Main oscillator runs. Sub oscillator runs. System clock is the main oscillation clock. Main oscillator runs (stops). Sub oscillator runs. System clock is the sub oscillation clock. Set SCMOD.2 to "1" Main oscillator still runs. CPU operates. Sub oscillator stops. Set SCMOD.2 to "1" Main oscillator still runs (stops). Sub oscillator stops, halting the CPU operation.
Set SCMOD.2 to "0" or reset
Reset
NOTES: 1. This mode must not be used. 2. Oscillation stabilization time by interrupt is 1/ (256 x BT clocks). Oscillation stabilization time by a reset is 31.3ms at 4.19Mhz, main oscillation clock.
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KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
Table 6-5. System Operating Mode Comparison Mode Main operating mode Condition Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Main oscillator runs. Sub oscillator runs. System clock is the main oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator runs. Sub oscillator is stopped by SCMOD.2. System clock is the main oscillation clock. STOP/IDLE Mode Start Method - Current Consumption A
Main Idle mode
IDLE instruction
B
Main Stop mode
STOP instruction
D
Sub operating mode
-
C
Sub ldle Mode
IDLE instruction
D
Sub Stop mode
Setting SCMOD.2 to "1": This mode can be released only by an external reset.
E
Main/Sub Stop mode
STOP instruction: This mode can be released by an interrupt and reset.
E
NOTE: The current consumption is: A > B > C > D > E.
6-9
OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
SWITCHING THE CPU CLOCK Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD, determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies. SCMOD.3, scmod.2, and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main or sub system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, 64, or fxt clock by 4. NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications -- the previously selected clock continues to run for a certain number of machine cycles. For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1". This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: First, clear SCMOD.3 to "0" to enable main system clock oscillation. Until main osc is stabilized, system clock must not be changed. Then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all SCMOD values to logic zero. Following a RESET, CPU operation starts with the lowest main system clock frequency of 15.3 sec at 4.19 MHz after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-6 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect.
6-10
KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
Table 6-6. Elapsed Machine Cycles During CPU Clock Switch
AFTER BEFORE PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 16 MACHINE CYCLES 16 MACHINE CYCLES N/A fx / 4fxt MACHINE CYCLE SCMOD.0 = 1 N/A N/A fx / 4fxt (M/C) N/A 8 MACHINE CYCLES N/A 8 MACHINE CYCLES N/A PCON.1 = 0 N/A PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 N/A SCMOD.0 = 1
1 MACHINE CYCLE
1 MACHINE CYCLE
NOTES: 1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered. 2. Since the XIN input is connected internally to VSS to avoid current leakage due to the crystal oscillator in stop mode, do 3. 4. 5. not set SCMOD.3 to "1" or STOP instruction when an external clock is used as the main system clock. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6-6. 'N/A' means 'not available'. fx: Main-system clock, fxt: Sub-system clock, M/C: Machine Cycle. When fx is 4.19 MHz, and fxt is 32.768 kHz.
+ PROGRAMMING TIP -- Switching Between Main System and Subsystem Clock 1. Switch from the main system clock to the subsystem clock: MA2SUB BITS CALL BITS RET LD NOP NOP DECS JR RET SCMOD.0 DLY80 SCMOD.3 A,#0FH ; Switches to subsystem clock ; Delay 80 machine cycles ; Stop the main system clock
DLY80 DEL1
A DEL1
2. Switch from the subsystem clock to the main system clock: SUB2MA BITR CALL CALL BITR RET SCMOD.3 DLY80 DLY80 SCMOD.0 ; ; ; ; Start main system clock oscillation Delay 80 machine cycles Delay 80 machine cycles Switch to main system clock
6-11
OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
CLOCK OUTPUT MODE REGISTER (CLMOD) The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions only. FD0H CLMOD.3 "0" CLMOD.1 CLMOD.0 CLMOD
RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without
initiating clock oscillation), and disables clock output. CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64. Table 6-7. Clock Output Mode Register (CLMOD) Organization CLMOD Bit Settings CLMOD.1 0 0 1 1 CLMOD.3 0 1 Clock output is disabled Clock output is enabled CLMOD.0 0 1 0 1 Clock Source CPU clock (fx/4, fx/8, fx/64, fxt/4) fxx/8 fxx/16 fxx/64 Result of CLMOD.3 Setting Resulting Clock Output Frequency 1.05 MHz, 524 kHz, 65.5 kHz 524 kHz 262 kHz 65.5 kHz
NOTE: Assumes that fxx = 4.19 MHz.
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KS57C2302/C2304/P2304 MICROCONTROLLER
OSCILLATOR CIRCUITS
CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: -- 4-bit clock output mode register (CLMOD) -- Clock selector -- Port mode flag -- CLO output pin (P2.2)
CLMOD.3 CLMOD.2
4
CLMOD.1 CLMOD.0
Clock Selector
P2.2 OUTPUT LATCH PM 2
CLO
clocks (fxx/8, fxx/16, fxx/64, CPU clock)
Figure 6-7. CLO Output Pin Circuit Diagram
CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the CLO pin may be summarized as follows: 1. Disable clock output by clearing CLMOD.3 to logic zero. 2. Set the clock output frequency (CLMOD.1, CLMOD.0). 3. Load "0" to the output latch of the CLO pin (P2.2). 4. Set the P2.2 mode flag (PM2) to output mode. 5. Enable clock output by setting CLMOD.3 to logic one.
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OSCILLATOR CIRCUITS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin: BITS SMB LD LD BITR LD LD EMB 15 EA,#04H PMG2,EA P2.2 A,#9H CLMOD,A
; P2 Output mode ; Clear P2.2 pin output latch
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INTERRUPTS
7
INTERRUPTS
OVERVIEW The KS57C2302/C2304interrupt control circuit has five functional components: -- Interrupt enable flags (IEx) -- Interrupt request flags (IRQx) -- Interrupt master enable register (IME) -- Interrupt priority register (IPR) -- Power-down release signal circuit Three kinds of interrupts are supported: -- Internal interrupts generated by on-chip processes -- External interrupts generated by external peripheral devices -- Quasi-interrupts used for edge detection and as clock sources
Table 7-1. Interrupt Types and Corresponding Port Pin(s) Interrupt Type External interrupts Internal interrupts Quasi-interrupts Interrupt Name INT0, INT1 INTB, INTT0 INT2, KS0-KS3 INTW Corresponding Port Pins P1.0, P1.1 Not applicable P1.2, P6.0-P6.3 Not applicable
7-1
INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. A vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (INTn) are set to logic one: -- Interrupt enable flag (IEx) -- Interrupt master enable flag (IME) -- Interrupt request flag (IRQx) -- Interrupt status flags (IS0, IS1) -- Interrupt priority register (IPR) If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction. The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the main routine, as well as during service routines. Any changes that are made to enable flag values during a service routine are not stored in the vector address. When an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the program status word (PSW), and the enable flag values for the interrupt is fetched from the respective vector address. Then, if necessary, you can modify the enable flags during the interrupt service routine. When the interrupt service routine is returned to the main routine by the IRET instruction, the original values saved in the stack are restored and the main program continues program execution with these values. Software-Generated Interrupts To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. Multiple Interrupts By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and thereby process multiple interrupts simultaneously. If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction. Power-Down Mode Release An interrupt (with the exception of INT0) can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases, the interrupt routine will not be executed since IME = "0".
7-2
KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPTS
Interrupt is generated. ( INT xx)
Request flag (IRQx) <-- 1
NO
IEx = 1 ? YES
Retains value until IEx =1
Generates the corresponding vector interrupt and releases power down mode.
NO
IME = 1 ? YES YES IS1,0 = 0, 0 ? NO IS1,0 = 0, 1 ? YES
Retains value until IME =1
Retains until interrupt service routine is completed.
NO
High priority interrupt ?
YES
NO
IS1,0 = 0,1
IS1,0 = 1,0
Stores the contents of PC and PSW in stack area; set PC contents to corresponding vector address.
Are both interrupt sources of shared vector address used? NO
YES
IRQx flag value remains 1
Reset corresponding IRQx flag
Jump to interrupt start address
Jump to interrupt start address
Verify interrupt source and clear IRQx with a BTSTZ instruction
Figure 7-1. Interrupt Execution Flowchart
7-3
INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
IMOD1
IMOD0
IE2 IEW IET0 IE1
IE0 IEB
INTB INT0 INT1
IRQB IRQ0 IRQ1
# @
@
INTT0 INTW INT2 SELECTOR KS0-KS3
IRQT0 IRQW IRQ2
IMOD2
POWER-DOWN MODE RELEASE
IME
IPR INTERRUPT CONTROL IS1 IS0
# = NOISE FILTERING CIRCUIT @ = EDGE DETECTION CIRCUIT
VECTOR INTERRUPT GENERATOR
Figure 7-2. Interrupt Control Circuit Diagram
7-4
KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPTS
MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. Two-Level Interrupt Handling Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see Figure 7-3). Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one, and the values are stored in the stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction. IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (EMB). Before you modify an interrupt service flag, however, you must first disable interrupt processing with a DI instruction. When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (IPR).
NORMAL PROGRAM PROCESSING (STATUS 0) INT DISABLE SET IPR INT ENABLE LOW OR HIGH LEVEL INTERRUPT GENERATED
HIGH OR LOW LEVEL INTERRUPT PROCESSING (STATUS 1) HIGH LEVEL INTERRUPT PROCESSING (STATUS 2)
HIGH-LEVEL INTERRUPT GENERATED
Figure 7-3. Two-Level Interrupt Handling
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INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
Multi-Level Interrupt Handling With multi-level interrupt handling, a lower-priority interrupt request can be executed by manipulating the interrupt status flags, IS0 and IS1 while a high-priority interrupt is being serviced (see Table 7-2). When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1" and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4).
Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling Process Status 0 1 2 - Before INT IS1 0 0 1 1 IS0 0 1 0 1 All interrupt requests are serviced. Only high-priority interrupts as determined by the current settings in the IPR register are serviced. No additional interrupt requests will be serviced. Value undefined Effect of ISx Bit Setting After INT ACK IS1 0 1 - - IS0 1 0 - -
NORMAL PROGRAM PROCESSING (STATUS 0) INT DISABLE SET IPR INT ENABLE LOW OR HIGH LEVEL INTERRUPT GENERATED MODIFY STATUS INT ENABLE LOW OR HIGH LEVEL INTERRUPT GENERATED INT DISABLE
SINGLE INTERRUPT 2-LEVEL INTERRUPT STATUS 1 3-LEVEL INTERRUPT
STATUS 0 HIGH-LEVEL INTERRUPT STATUS 1 STATUS 2 GENERATED
STATUS 0
Figure 7-4. Multi-Level Interrupt Handling
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KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPTS
INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction. FB2H IME IPR.2 IPR.1 IPR.0
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. Table 7-3. Standard Interrupt Priorities Interrupt INTB INT0 INT1 INTT0 Default Priority 1 2 3 4
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the IME flag is set to logic one. The IME flag (mapped FB2H.3) can be directly manipulated by EI and DI instructions, regardless of the current enable memory bank (EMB) value. Table 7-4. Interrupt Priority Register Settings IPR.2 0 0 0 0 1 1 IPR.1 0 0 1 1 0 0 IPR.0 0 1 0 1 0 1 Result of IPR Bit Setting Normal interrupt handling according to default priority settings Process INTB interrupt at highest priority Process INT0 interrupt at highest priority Process INT1 interrupt at highest priority Reserved Process INTT0 interrupt at highest priority
NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in Table 7-3 (the default priority assigned by hardware when the lower three IPR bits = "0"). In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started.
7-7
INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Setting the INT Interrupt Priority
The following instruction sequence sets the INT1 interrupt to high priority: BITS SMB DI LD LD EI EMB 15 A,#3H IPR,A
; IPR.3 (IME) 0 ; IPR.3 (IME) 1
EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS (IMOD0 and IMOD1) The following components are used to process external interrupts at the INT0 and INT1 pins: -- Noise filtering circuit for INT0 -- Edge detection circuit -- Two mode registers, IMOD0 and IMOD1 The mode registers are used to control the triggering edge of the input signal. IMOD0 and IMOD1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. Since INT2 is a quasi-interrupt, the interrupt request flag (IRQ2) must be cleared by software. FB4H FB5H IMOD0.3 "0" "0" "0" IMOD0.1 "0" IMOD0.0 IMOD1.0
IMOD0 and IMOD1 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. Table 7-5. IMOD0, 1 and 2 Register Organization IMOD0 IMOD0.3 0 1 0 0 1 1 IMOD1 0 0 0 0 1 0 1 IMOD1.0 0 1 0 IMOD0.1 IMOD0.0 Effect of IMOD0 Settings Select CPU clock for sampling Select fxx/64 sampling clock Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1" Effect of IMOD1 Settings Rising edge detection Falling edge detection
7-8
KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPTS
EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS (Continued) When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: -- To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of the clock selected by IMOD0.
INT0 P1.0
NOISE FILTER
EDGE
IRQ0
CLOCK SELECTOR
IRQ1
CPU Clock INT1
fxx/64 EDGE
IMOD0 P1.1
IMOD1
Figure 7-5. Circuit Diagram for INT0 and INT1 Pins When modifying the IMOD registers, it is possible to accidentally set an interrupt request flag. To avoid unwanted interrupts, take these precautions when writing your programs: 1. Disable all interrupts with a DI instruction. 2. Modify the IMOD register. 3. Clear all relevant interrupt request flags. 4. Enable the interrupt by setting the appropriate IEx flag. 5. Enable all interrupts with an EI instructions.
7-9
INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
EXTERNAL INTERRUPT 2 MODE REGISTER (IMOD2) The mode register for external interrupt 2 at the KS0-KS3 pins, IMOD2, is addressable only by 4-bit write instructions. RESET clears all IMOD2 bits to logic zero. FB6H "0" "0" IMOD2.1 IMOD2.0
If a rising or falling edge is detected at any one of the selected KS pin by the IMOD2 register, the IRQ2 flag is set to logic one and a release signal for power-down mode is generated. Table 7-6. IMOD2 Register Bit Settings IMOD2 0 0 IMOD2.1 0 0 1 1 IMOD2.0 0 1 0 1 Effect of IMOD2 Settings Select rising edge at INT2 pin Reserved Select falling edge at KS2-KS3 Select falling edge at KS0-KS3
7-10
KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPTS
INT2
Rising Edge Detection Circuit
P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 Falling Edge Detection Circuit
Selector IMOD2
IRQ2
Figure 7-6. Circuit Diagram for INT2 and KS0-KS3 Pins
7-11
INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPT FLAGS There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt, the interrupt master enable flag, which enables or disables all interrupt processing. Interrupt Master Enable Flag (IME) The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag is set to logic one. The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB). FB2H IME 0 1 Interrupt Enable Flags (IEx) IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled. Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag. Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses Address FB8H FBAH FBCH FBEH FBFH Bit 3 0 0 0 IE1 0 Bit 2 0 0 0 IRQ1 0 Bit 1 IEB IEW IET0 IE0 IE2 Bit 0 IRQB IRQW IRQT0 IRQ0 IRQ2 IPR.2 IPR.1 IPR.0 Effect of Bit Settings Inhibit all interrupts Allow all interrupts
NOTES: 1. IEx refers generally to all interrupt enable flags. 2. IRQx refers generally to all interrupt request flags. 3. IEx = 0 is interrupt disable mode. 4. IEx = 1 is interrupt enable mode.
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KS57C2302/C2304/P2304 MICROCONTROLLER
INTERRUPTS
Interrupt Request Flags (IRQx) Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag. When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary, follow these guidelines for using IRQx flags: 1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of IRQW and IRQ2). 3. When IRQx is set to "1" by software, an interrupt is generated.
Table 7-8. Interrupt Request Flag Conditions and Priorities Interrupt Source INTB INT0 INT1 INTT0 INT2
(note)
Internal / External I E E I E I
Pre-condition for IRQx Flag Setting Reference time interval signal from basic timer Rising or falling edge detected at INT0 pin Rising or falling edge detected at INT1 pin Signals for TCNT0 and TREF0 registers match Rising edge detected at INT2 Time interval of 0.5 secs or 3.19 msecs
Interrupt Priority 1 2 3 4 - -
IRQ Flag Name IRQB IRQ0 IRQ1 IRQT0 IRQ2 IRQW
INTW
NOTE: The quasi-interrupt INT2 is only used for testing incoming signals.
7-13
INTERRUPTS
KS57C2302/C2304/P2304 MICROCONTROLLER
NOTES
7-14
KS57C2302/C2304/P2304 MICROCONTROLLER
POWER-DOWN
8
POWER-DOWN
OVERVIEW The KS57C2302/C2304 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed, normal CPU operation resumes. In main stop mode, main system clock oscillation is halted (assuming main clock is selected as system clock and it is currently operating), and peripheral hardware components are powered-down. In sub stop mode, (assuming sub clock is selected) sub system clock oscillation is halted by setting SCMOD.2 to "1". The effect of stop mode on specific peripheral hardware components -- CPU, basic timer, timer/ counter 0, watch timer, and LCD controller -- and on external interrupt requests, is detailed in Table 8-1. NOTE Do not use stop mode if you are using an external clock source because Xin input must be restricted internally to VSS to reduce current leakage. Idle or main stop modes are terminated either by a RESET, or by an interrupt which is enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. Sub stop mode can be terminated by RESET only. When an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (IME): -- If the IME flag = "0", program execution starts immediately after the instruction issuing a request to enter power-down mode is executed. The interrupt request flag remains set to logical one. -- If the IME flag = "1", two instructions are executed after the power-down mode release and the vectored interrupt is then initiated. However, when the release signal is caused by INT2 or INTW, the operation is identical to the IME = "0" condition. Assuming that both interrupt enable flag and interrupt request flag are set to "1", the release signal is generated when power-down mode is entered.
8-1
POWER-DOWN
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 8-1. Hardware Operation During Power-Down Modes Mode System clock Instruction Clock oscillator Basic timer Timer/counter 0 Main Stop Main clock (fx) STOP Main clock oscillation stops Basic timer stops. Operates only if TCL0 is selected as counter clock. Operates only if sub clock (fxt) is selected as counter clock. Operates only if sub clock (fxt) is selected as LCD clock, LCDCK. INT1 and INT2 are acknowledged; INT0 is not serviced. Sub Stop Sub clock (fxt) Setting SCMOD.2 to "1" Sub clock oscillation stops Basic timer stops. Operates only if TCL0 is selected as counter clock. Watch timer stops. Main/Sub Stop Main clock (fx) STOP Main clock oscillation stops Basic timer stops. Operates only if TCL0 is selected as counter clock. Watch timer stops.
(1)
Idle Main (fx) or sub clock (fxt) IDLE Only CPU clock stops. (2) Basic timer operates. Timer/counter 0 operates. Watch timer operates. LCD controller operates.
Watch timer
LCD controller
LCD controller stops.
LCD controller stops.
External interrupts CPU Mode release signal
INT0, INT1, and INT2 INT1 and INT2 are is not serviced. acknowledged; INT0 is not serviced.
INT1 and INT2 are acknowledged; INT0 is not serviced.
All CPU operations are disabled. Interrupt request Only RESET input signals (except INT0) pre-enabled by IEx or RESET input. Interrupt request signals (except INT0) preenabled by IEx or RESET input.
NOTE: 1. Sub clock stops by setting SCMOD.2 to "1". 2. Main and sub clock oscillation continues.
8-2
KS57C2302/C2304/P2304 MICROCONTROLLER
POWER-DOWN
IDLE MODE TIMING DIAGRAMS
IDLE INSTRUCTION
RESET
OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz)
NORMAL MODE
IDLE MODE
NORMAL MODE
CLOCK SIGNAL
NORMAL OSCILLATION
Figure 8-1. Timing When Idle Mode is Released by RESET
IDLE INSTRUCTION MODE RELEASE SIGNAL NORMAL MODE IDLE MODE INTERRUPT ACKNOWLEDGE (IME = 1)
NORMAL MODE
CLOCK SIGNAL
NORMAL OSCILLATION
Figure 8-2. Timing When Idle Mode is Released by an Interrupt
8-3
POWER-DOWN
KS57C2302/C2304/P2304 MICROCONTROLLER
STOP MODE TIMING DIAGRAMS
STOP INSTRUCTION
RESET
OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz)
NORMAL MODE
STOP MODE
IDLE MODE
NORMAL MODE
CLOCK SIGNAL
OSCILLATION STOPS
OSCILLATION RESUMES
Figure 8-3. Timing When Stop Mode is Released by RESET
STOP INSTRUCTION MODE RELEASE SIGNAL NORMAL MODE STOP MODE OSCILLATION STOPS
OSCILLATION STABILIZATION (BMOD SETTING) INT ACK (IME = 1)
IDLE MODE
NORMAL MODE
CLOCK SIGNAL
OSCILLATION RESUMES
Figure 8-4. Timing When Main Stop or Main/Sub Stop Mode is Release by an Interrupt
8-4
KS57C2302/C2304/P2304 MICROCONTROLLER
POWER-DOWN
+ PROGRAMMING TIP -- Reducing Power Consumption for Key Input Interrupt Processing
The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. In this example, the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on: KEYCLK DI CALL SMB LD LD LD LD SMB BITR BITR BITS BITS CALL BTSTZ JR CALL EI RET IDLE NOP NOP NOP JPS MA2SUB 15 EA,#00H P2,EA A,#3H IMOD2,A 0 IRQW IRQ2 IEW IE2 WATDIS IRQ2 CIDLE SUB2MA ; Main system clock subsystem clock switch subroutine
; All key strobe outputs to low level ; Select KS0-KS3 enable
CLKS1
; Execute clock and display changing subroutine ; Subsystem clock main system clock switch
subroutine
CIDLE
; Engage idle mode
CLKS1 NOTE
You must execute three NOP instructions after IDLE and STOP instructions, to avoid flowing of leakage current due to the floating state in the internal bus.
8-5
POWER-DOWN
KS57C2302/C2304/P2304 MICROCONTROLLER
PORT PIN CONFIGURATION FOR POWER-DOWN The following method describes how to configure I/O port pins to reduce power consumption during power-down modes (stop, idle): Condition 1: If the microcontroller is not configured to an external device:
1. Connect unused port pins according to the information in Table 8-2. 2. Disable pull-up resistors for input pins configured to VDD or VSS levels in order to check the current input option. Reason: If the input level of a port pin is set to VSS when a pull-up resistor is enabled, it will draw an unnecessarily large current. Condition 2: If the microcontroller is configured to an external device and the external device's VDD source is turned off in power-down mode.
1. Connect unused port pins according to the information in Table 8-2. 2. Disable pull-up resistors for input pins configured to VDD or VSS levels in order to check the current input option. Reason: If the input level of a port pin is set to VSS when a pull-up resistor is enabled, it will draw an unnecessarily large current. 3. Disable the pull-up resistors of input pins connected to the external device by making the necessary modifications to the PUMOD register. 4. Configure the output pins that are connected to the external device to low level. Reason: When the external device's VDD source is turned off, and if the microcontroller's output pins are set to high level, VDD - 0.7 V is supplied to the VDD of the external device through its input pin. This causes the device to operate at the level VDD - 0.7 V. In this case, total current consumption would not be reduced. 5. Determine the correct output pin state necessary to block current pass in according with the external transistors (PNP, NPN).
8-6
KS57C2302/C2304/P2304 MICROCONTROLLER
POWER-DOWN
RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 8-2. Table 8-2. Unused Pin Connections for Reducing Power Consumption Pin/Share Pin Names P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.2-P3.3 P3.1/LCDSY P3.0/LCDCK P8.0/SEG24-P8.7/SEG31 SEG0-SEG23 COM0-COM3 VLC0-VLC2 XTin XTout TEST
NOTES: 1. Digital mode at P1.0 and P1.1 2. Used as segment
Recommended Connection Connect to VDD
(1)
Input mode: Connect to VDD Output mode: No connection
Input mode: Connect to VDD Output mode: No connection No connection (2) No connection No connection Connect XTin to VSS and set SCMOD.2 to "1" No connection Connect to VSS
8-7
POWER-DOWN
KS57C2302/C2304/P2304 MICROCONTROLLER
NOTES
8-8
KS57C2302/ C2304/P2304 MICROCONTROLLER
RESET
9
RESET
OVERVIEW When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has elapsed, normal system operation resumes. Regardless of when the RESET occurs -- during normal operating mode or during a power-down mode -- most hardware register values are set to the reset values described in Table 9-1. The current status of several register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs during normal operating mode, their values are undefined. Current values that are retained in this case are as follows: -- Carry flag -- Data memory values -- General-purpose registers E, A, L, H, X, W, Z, and Y
OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz)
RESET
INPUT
NORMAL MODE OR POWER-DOWN MODE
RESET
IDLE MODE
OPERATING MODE
OPERATION
Figure 9-1. Timing for Oscillation Stabilization After RESET
HARDWARE REGISTER VALUES AFTER RESET Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-down mode or during normal operation.
9-1
RESET
KS57C2302/ C2304/P2304 MICROCONTROLLER
Table 9-1. Hardware Register Values After RESET Hardware Component or Subcomponent Program counter (PC) If RESET Occurs During Power-Down Mode Lower four bits of address 0000H are transferred to PC11-8, and the contents of 0001H to PC7-0. If RESET Occurs During Normal Operation Lower four bits of address 0000H are transferred to PC11-8, and the contents of 0001H to PC7-0.
Program Status Word (PSW): Carry flag (C) Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Retained 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Undefined 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined
Stack pointer (SP) Data Memory (RAM): Working registers E, A, L, H, X, W, Z, Y General-purpose registers Bank selection registers (SMB, SRB) BSC register (BSC0-BSC3) Clocks: Power control register (PCON) Clock output mode register (CLMOD) System clock control reg (SCMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INT2 mode register (IMOD2)
Values retained Values retained 0, 0 0
Undefined Undefined 0, 0 0
0 0 0
0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
9-2
KS57C2302/ C2304/P2304 MICROCONTROLLER
RESET
Table 9-1. Hardware Register Values After RESET (Continued) Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD) Basic Timer: Count register (BCNT) Mode register (BMOD) Timer/Counter 0: Count registers (TCNT0) Reference registers (TREF0) Mode registers (TMOD0) Output enable flags (TOE0) Watchdog Timer: WDT mode register (WDMOD) WDT clear flag (WDTCF) Watch Timer: Watch timer mode register (WMOD) LCD Driver/Controller: LCD mode register (LMOD) LCD control register (LCON) Display data memory Output buffers 0 0 Values retained Off 0 0 Undefined Off 0 0 A5H 0 A5H 0 0 FFH 0 0 0 FFH 0 0 Undefined 0 Undefined 0 Off 0 0 0 Off 0 0 0 If RESET Occurs During Power-Down Mode If RESET Occurs During Normal Operation
9-3
RESET
KS57C2302/ C2304/P2304 MICROCONTROLLER
NOTES
9-4
KS57C2302/C2304/P2304 MICROCONTROLLER
I/O PORTS
10
OVERVIEW Port Mode Flags
I/O PORTS
The KS57C2302/C2304 has 5 ports. There are total of 4 input pins, 8 output pins and 12 configurable I/O pins, for a maximum number of 24 pins. Pin addresses for all ports are mapped to bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions.
Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. Pull-Up Resistor Mode Register (PUMOD) The pull-up mode registers (PUMOD) are used to assign internal pull-up resistors by software to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
10-1
I/O PORTS
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 10-1. I/O Port Overview Port 1 I/O I Pins 4 Pin Names P1.0-P1.3 Address FF1H Function Description 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. Port 3 pins are individually software configurable as input or output. 1-, and 4-bit read/write/test is possible. 4-bit pullup resistors are software assignable. 4-bit I/O port. Port 6 pins are individually software configurable as input or output. 1-, and 4-bit read/write/test is possible. 4-bit pullup resistors are software assignable. Output port for 1-bit data (for use as CMOS driver only)
2
I/O
4
P2.0-P2.3
FF2H
3
I/O
4
P3.0-P3.3
FF3H
6
I/O
4
P6.0-P6.3
FF6H
8
O
8
P8.0-P8.7
1F8H-1FFH
Table 10-2. Port Pin Status During Instruction Execution Instruction Type 1-bit test 1-bit input 4-bit input 1-bit output 4-bit output Example BTST LDB LD BITR LD P0.1 C,P1.3 A,P1 P2.3 P2,A Input Mode Status Input or test data at each pin Output Mode Status Input or test data at output latch
Output latch contents undefined Transfer accumulator data to the output latch
Output pin status is modified Transfer accumulator data to the output pin
10-2
KS57C2302/C2304/P2304 MICROCONTROLLER
I/O PORTS
PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. For convenient program reference, PM flags are organized into two groups -- PMG1 and PMG2 as shown in Table 10-3. They are addressable by 8-bit write instructions only. When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears all port mode flags to logical zero, automatically configuring the corresponding I/O ports to input mode. Table 10-3. Port Mode Group Flags PM Group ID PMG1 PMG2 Address FE8H FE9H FECH FEDH Bit 3 PM3.3 PM6.3 "0" "0" Bit 2 PM3.2 PM6.2 PM2 "0" Bit 1 PM3.1 PM6.1 "0" "0" Bit 0 PM3.0 PM6.0 "0" "0"
+ PROGRAMMING TIP -- Configuring I/O Ports to Input or Output
Configure ports 3 and 6 as an output port: BITS SMB LD LD EMB 15 EA,#0FFH PMG1,EA
; P3 and P6 Output
PULL-UP RESISTOR MODE REGISTER (PUMOD) The pull-up resistor mode register (PUMOD) is used to assign internal pull-up resistors by software to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting. PUMOD is addressable by 8-bit write instructions only. RESET clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors. Table 10-4. Pull-Up Resistor Mode Register (PUMOD) Organization PUMOD ID PUMOD Address FDCH FDDH Bit 3 PUR3 "0" Bit 2 PUR2 PUR6 Bit 1 PUR1 "0" Bit 0 "0" "0"
NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2, and so on.
10-3
I/O PORTS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Enabling and Disabling I/O Port Pull-Up Resistors
P2 and P3 are enabled to have pull-up resistors. BITS SMB LD LD EMB 15 EA,#0CH PUMOD,EA
; Enable P2 and P3 to have pull-up resistors
PIN ADDRESSING FOR OUTPUT PORT 8 The addresses for the port 8 1-bit output pin buffers are located in bank 1 of data memory instead of bank 15. To address port 8 output pins, use the settings EMB = 1 and SMB = 1. The LCD mode register, LMOD is used to control whether the pin address is used for LCD data output or for normal data output: Table 10-5. LMOD.7 and LMOD.6 Setting for Port 8 Output Control LMOD.7 0 0 1 1 LMOD.6 0 1 0 1 LCD Output Segments Seg 24-31 Seg 24-27 Seg 28-31 - 1-Bit Output Pins - P8.4-P8.7 (Seg 28-31) P8.0-P8.3 (Seg 24-27) P8.0-P8.7 (Seg 24-31)
Each address in RAM bank 1 corresponds to a 4-bit register location. The LSB (bit 0) of the register location is used as the port buffer for either LCD segment output or normal 1-bit data output. Locations that are unused for LCD or port I/O can be used as normal data memory. After a RESET, the values contained in the port 8 output buffer are left undetermined. Table 10-6 shows port 8 pin addresses and also the corresponding LCD segment names if the pins are used to output LCD segment data. Pin addresses that are not used for LCD segment output can be used for normal 1-bit output. Table 10-6. Port 8 Pin Addresses and LCD Segment Correspondence Port 8 Pin Number P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 RAM Address 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH LCD Segment SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
10-4
KS57C2302/C2304/P2304 MICROCONTROLLER
I/O PORTS
PORT 1 CIRCUIT DIAGRAM
V DD
INT0 INT1 INT2 TCL0
PUMOD.1
IMOD0
P1.0
N/R Circuit
P1.1 P1.2 P1.3
INT0
NOISE FILTER
EDGE
IRQ0
P1.0
CLOCK SELECTOR
IRQ1
CPU clock INT1
fxx/64 EDGE
IMOD0 P1.1
IMOD1
Figure 10-1. Input Port 1 Circuit Diagram
10-5
I/O PORTS
KS57C2302/C2304/P2304 MICROCONTROLLER
PORT 2 CIRCUIT DIAGRAM
VDD VDD VDD VDD
PUMOD.2
PM2
8
P2.0 P2.1 P2.2 P2.3
OUTPUT LATCH
1, 4
M U X
1, 4
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 10-2. Port 2 Circuit Diagram
10-6
KS57C2302/C2304/P2304 MICROCONTROLLER
I/O PORTS
PORTS 3 AND 6 CIRCUIT DIAGRAM
VDD
PUMOD.x
x = port number (3, 6)
PMx.3
PMx.2
PMx.1
PMx.0
Px.0 Px.1 Px.2 Px.3 OUTPUT LATCH 1, 4
M U X 1, 4
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 10-3. Ports 3 and 6 Circuit Diagram
10-7
I/O PORTS
KS57C2302/C2304/P2304 MICROCONTROLLER
NOTES
10-8
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
11
OVERVIEW -- Watch timer (WT)
TIMERS and TIMER/COUNTERS
The KS57C2302/C2304 microcontroller has three timer and timer/counter modules: -- 8-bit basic timer (BT) -- 8-bit timer/counter (TC0)
The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. The basic timer also functions as `watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET. The 8-bit timer/counter (TC0) is programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. It also generates a clock signal for the LCD controller.
11-1
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
BASIC TIMER (BT)
OVERVIEW The 8-bit basic timer (BT) has five functional components: -- Clock selector logic -- 4-bit mode register (BMOD) -- 8-bit counter register (BCNT) -- 8-bit watchdog timer mode register (WDMOD) -- Watchdog timer counter clear flag (WDTCF) The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. Basic timer's counter register, BCNT, outputs timer pulses to the watchdog timer's counter register, WDTCNT when an overflow occurs in BCNT. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET. Bit settings in the basic timer mode register BMOD turns the BT on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. Interval Timer Function The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT clock pulses. To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2-BMOD.0. The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs. An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting continues from 00H. Oscillation Stabilization Interval Control Bits 2-0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also determines the time interval (also referred to as `wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. When a RESET signal is generated, the standard stabilization interval for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz. Watchdog Timer Function The basic timer can also be used as a "watchdog" timer to detect an inadvertent program loop, that is, system or program operation error. For this purpose, instruction that clears the watchdog timer (BITS WDTCF) within a given period should be executed at proper points in a program. If an instruction that clears the watchdog timer is not done within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. An operation of watchdog timer is as follows: -- Write some value (except #5AH) to Watchdog Timer Mode register, WDMOD. -- Each time BCNT overflows, an overflow signal is sent to the watchdog timer counter, WDCNT. -- If WDTCNT overflows, system reset will be generated.
11-2
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
Table 11-1. Basic Timer Register Overview Register Name BMOD Type Control Description Controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or RESET Counts clock pulses matching the BMOD frequency setting Controls watchdog timer operation. Clear the watchdog timer's counter. Size 4-bit RAM Address F85H Addressing Mode 4-bit write-only; BMOD.3: 1-bit write-only 8-bit readonly 8-bit write-only 1-bit write-only Reset Value "0"
BCNT WDMOD WDTCF
Counter Control Control
8-bit 8-bit 1-bit
F86H-F87H F98H-F99H F9AH.3
"u"
(note)
A5H "0"
NOTE: "u" means that the value is undetermined after a RESET.
"Clear" Signal Clear BCNT Overflow BCNT Bit5 Clear IRQB Interrupt Request 1-Bit R/W Cpu Clock Start Signal (By Interrupts) (By RESET )
Bits Instruction 4
BMOD.3 BMOD.2 BMOD.1 BMOD.0 8 Clock Input Clock Selector
IRQB
1 pulse period=BT input clock 2 8 (1/2 duty) 3-Bit Counter WDTCNT C WDMOD Overflow Reset Generation
RESET
8 WDTCF Wait
RESET
DELAY Clear
Stop
Bits Instruction
NOTE: WAIT means stabilization time after RESET or Stabilization time after STOP mode release.
Figure 11-1. Basic Timer Circuit Diagram
11-3
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also 1-bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following effects: -- Restart the basic timer; -- Control the frequency of clock signal input to the basic timer; -- Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency during program execution. Four BT frequencies, ranging from fxx/212 to fxx/25, are selectable. Since BMOD's reset value is logic zero, the default clock frequency setting is fxx/212. The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted. The combination of bit settings in the remaining three registers -- BMOD.2, BMOD.1, and BMOD.0 -- determines the clock input frequency and oscillation stabilization interval. Table 11-2. Basic Timer Mode Register (BMOD) Organization BMOD.3 1 Basic Timer Restart Bit Restart basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2 0 0 1 1
BMOD.1 0 1 0 1
BMOD.0 0 1 1 1
Basic Timer Input Clock fxx/212 (1.02 kHz) fxx/29 (8.18 kHz) fxx/27 (32.7 kHz) fxx/25 (131 kHz)
Interval Time 220/fxx (250 ms) 217/fxx (31.3 ms) 215/fxx (7.82 ms) 213/fxx (1.95 ms)
NOTES: 1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 MHz. 2. fxx = selected system clock frequency. 3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. The data in the table column 'Oscillation Stabilization' can also be interpreted as "Interrupt Interval Time." 4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
11-4
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. leaves the BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected.
RESET
When BCNT has incremented to hexadecimal 'FFH' (255 clock pulses), it is cleared to '00H' and an overflow is generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt request is generated, BCNT immediately resumes counting with incoming clock signal. NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the latter value as valid data. Until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met.
BASIC TIMER OPERATION SEQUENCE The basic timer's sequence of operations may be summarized as follows: 1. Set counter buffer bit (BMOD.3) to logic one to restart the basic timer. 2. BCNT is then incremented by one per each clock pulse corresponding to BMOD selection. 3. BCNT overflows if BCNT = 255 (BCNT = FFH). 4. When an overflow occurs, the IRQB flag is set by hardware to logic one. 5. The interrupt request is generated. 6. BCNT is then cleared by hardware to logic zero. 7. Basic timer resumes counting clock pulses.
11-5
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Using the Basic Timer
1. To read the basic timer count register (BCNT): BITS SMB LD LD LD CPSE JR EMB 15 EA,BCNT YZ,EA EA,BCNT EA,YZ BCNTR
BCNTR
2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: BITS SMB LD LD NOP STOP NOP NOP NOP EMB 15 A,#0BH BMOD,A
; Wait time is 31.3 ms ; Set stop power-down mode
CPU OPERATION
NORMAL OPERATING MODE
STOP MODE
IDLE MODE (31.3 ms)
NORMAL OPERATING MODE
STOP INSTRUCTION
STOP MODE IS RELEASED BY INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz): BITS SMB LD LD EI BITS EMB 15 A,#0FH BMOD,A IEB ; Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer: BITS SMB BITS EMB 15 BMOD.3
11-6
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
WATCHDOG TIMER MODE REGISTER (WDMOD) The watchdog timer mode register, WDMOD, is a 8-bit write-only register located at RAM address F98H-F99H. WDMOD register controls to enable or disable the watchdog function. WDMOD values are set to logic "A5H" following RESET and this value enables the watchdog timer, and watchdog timer is set to the longest interval because BT overflow signal is generated with the longest interval. WDMOD 5AH Any other value Watchdog Timer Enable/Disable Control Disable watchdog timer function Enable watchdog timer function
WATCHDOG TIMER COUNTER (WDCNT) The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and restarts whenever the WDTCF register control bit is set to "1". RESET, stop, and wait signal clears the WDCNT to logic zero also. WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated. When WDCNT has incremented to hexadecimal `07H', it is cleared to `00H' and an overflow is generated. The overflow causes the system RESET. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF) The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears the WDCNT to zero and restarts the WDCNT. WDTCF register bits 2-0 are always logic zero. Table 11-3. Watchdog Timer Interval Time BMOD x000b BT Input Clock (frequency) fxx/212 fxx/29 fxx/27 fxx/25 WDCNT Input Clock (frequency) fxx/(212 x 28) fxx/(29 x 28) fxx/(27 x 28) fxx/(25 x 28) WDT Interval Time 212 x 28 x 23/fxx 29 x 28 x 23/fxx 27 x 28 x 23/fxx 25 x 28 x 23/fxx Main Clock 1.75-2 sec 218.7-250 ms 54.6-62.5 ms 13.6-15.6 ms Sub Clock 224-256 sec 28-32 sec 7-8 sec 1.75-2 sec
x011b
x101b
x111b
NOTES: 1. Clock frequencies assume a system oscillator clock frequency (fxx) of: 4.19 MHz Main clock or 32.768 kHz Sub clock 2. fxx = system clock frequency. 3. If the WDMOD changes such as disable and enable, you must set WDTCF flag to "1" for starting WDCNT from zero state.
11-7
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Using the Watchdog Timer
RESET
DI BITS SMB LD LD
LD LD
MAIN
BITS
EMB 15 EA,#00H SP,EA * * * A,#0DH BMOD,A * * * WDTCF * * * MAIN
; WDCNT input clock is 7.82 ms
; Main routine operation period must be shorter than ; watchdog ; timer's period
JP
11-8
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
8-BIT TIMER/COUNTER 0 (TC0)
OVERVIEW Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC0 can be used to measure specific time intervals. TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by counter logic. An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into the TMOD0 register during program execution. TC0 FUNCTION SUMMARY 8-bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency. Counts various system "events" based on edge detection of external clock signals at the TC0 input pin, TCL0. To start the event counting operation, TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0". Outputs selectable clock frequencies to the TC0 output pin, TCLO0. Divides the frequency of an incoming external clock signal according to a modifiable reference value (TREF0), and outputs the modified frequency to the TCLO0 pin.
External event counter
Arbitrary frequency output External signal divider
11-9
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
TC0 COMPONENT SUMMARY Mode register (TMOD0) Activates the timer/counter and selects the internal clock frequency or the external clock source at the TCL0 pin. Stores the reference value for the desired number of clock pulses between interrupt requests. Counts internal or external clock pulses based on the bit settings in TMOD0 and TREF0. Together with the mode register (TMOD0), lets you select one of four internal clock frequencies or an external clock. Determines when to generate an interrupt by comparing the current value of the counter register (TCNT0) with the reference value previously programmed into the reference register (TREF0). Where a clock pulse is stored pending output to the TC0 output pin, TCLO0. When the contents of the TCNT0 and TREF0 registers coincide, the timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is inverted, and an interrupt is generated. Output enable flag (TOE0) Must be set to logic one before the contents of the TOL0 latch can be output to TCLO0. Cleared when TC0 operation starts and the TC0 interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide. Must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed.
Reference register (TREF0)
Counter register (TCNT0)
Clock selector circuit
8-bit comparator
Output latch (TOL0)
Interrupt request flag (IRQT0)
Interrupt enable flag (IET0)
11-10
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
Table 11-4. TC0 Register Overview Register Name TMOD0 Type Control Description Controls TC0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6-4) Counts clock pulses matching the TMOD0 frequency setting Stores reference value for the timer/counter 0 interval setting Controls timer/counter 0 output to the TCLO0 pin Size 8-bit RAM Address F90H-F91H Addressing Mode 8-bit write-only; (TMOD0.3 is also 1-bit writeable) 8-bit read-only 8-bit write-only 1-bit write-only Reset Value "0"
TCNT0 TREF0 TOE0
Counter Reference Flag
8-bit 8-bit 1-bit
F94H-F95H F96H-F97H F92H.2
"0" FFH "0"
P1.3 TCL0 TMOD0.7 TMOD0.6 TMOD0.5 8 TMOD0.4 TMOD0.3 TMOD0.2 TMOD0.1
Clocks 4 (Fxx/210, Fxx/28 , Fxx/26 , Fxx/2 )
8 TCNT0 Clock Selector 8-Bit Comparator
8 TREF0
Clear
Inverted TMOD0.0 Clear IRQT0 TCLO0 Set Clear TOL0
PM2
P2.0 LATCH
TOE0
Figure 11-2. TC0 Circuit Diagram
11-11
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 -- Set TMOD0.2 to logic one -- Set the TC0 interrupt enable flag IET0 to logic one -- Set TMOD0.3 to logic one TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts. Disable Timer/Counter 0 -- Set TMOD0.2 to logic zero Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read if necessary.
11-12
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated. To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF0 register. TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD0.4-TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag (IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H and TC0 continues counting. The interrupt request mechanism for TC0 includes an interrupt enable flag (IET0) and an interrupt request flag (IRQT0).
TC0 OPERATION SEQUENCE The general sequence of operations for using TC0 can be summarized as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Set TMOD0.2 to "1" to enable TC0. Set TMOD0.6 to "1" to enable the system clock (fxx) input. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fxx/2n). Load a value to TREF0 to specify the interval between interrupt requests. Set the TC0 interrupt enable flag (IET0) to "1". Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting. TCNT0 increments with each internal clock pulse. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1" and an interrupt request is generated. Output latch (TOL0) logic toggles high or low.
10. TCNT0 is cleared to 00H and counting resumes. 11. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".
11-13
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
TC0 EVENT COUNTER FUNCTION Timer/counter 0 can monitor or detect system 'events' by using the external clock input at the TCL0 pin as the counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs. With the exception of the different TMOD0.4-TMOD0.6 settings, the operation sequence for TC0's event counter function is identical to its programmable timer/counter function. To activate the TC0 event counter function, -- Set TMOD0.2 to "1" to enable TC0; -- Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin; -- Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5 and TMOD0.4.
Table 11-5. TMOD0 Settings for TCL0 Edge Detection TMOD0.5 0 0 TMOD0.4 0 1 TCL0 Edge Detection Rising edges Falling edges
11-14
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected by loading the desired reference value into the reference register TREF0. To enable the output to the TCLO0 pin, the following conditions must be met: -- TC0 output enable flag TOE0 must be set to "1" -- I/O mode flag for P2.0 must be set to output mode ("1") -- Output latch value for P2.0 must be set to "0" In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as follows: 1. Load a reference value to TREF0. 2. Set the internal clock frequency in TMOD0. 3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1"). 4. Set P2.0 mode flag to "1". 5. Set P2.0 output latch to "0". 6. Set TOE0 flag to "1". Each time TCNT0 overflows and an interrupt request is generated, the state of the output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.
+ PROGRAMMING TIP -- TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin: BITS SMB LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA EA,#04H PMG2,EA P2.0 TOE0
; P2.0 output mode ; P2.0 clear
11-15
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
TC0 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows: 1. Load a signal divider value to the TREF0 register. 2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin. 3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection. 4. Set port 2.0 mode flag (PM2) to output ("1"). 5. Set P2.0 output latch to "0". 6. Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin
+ PROGRAMMING TIP -- External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divided by four):
EXTERNAL (TCL0) CLOCK PULSE
TCLO0 OUTPUT PULSE
BITS SMB LD LD LD LD LD LD BITR BITS
EMB 15 EA,#01H TREF0,EA EA,#0CH TMOD0,EA EA,#04H PMG2,EA P2.0 TOE0
; P2.0 output mode ; P2.0 clear
11-16
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations. F90H F91H TMOD0.3 "0" TMOD0.2 TMOD0.6 "0" TMOD0.5 "0" TMOD0.4
TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are retained until TC0 is re-enabled. The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This selection involves two variables: -- Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input at the TCL0 pin, and -- Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal TC0 operation.
Table 11-6. TC0 Mode Register (TMOD0) Organization Bit Name TMOD0.7 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.3 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes.) Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0 Always logic zero Always logic zero F90H Setting 0 0,1 Always logic zero Specify input clock edge and internal frequency Resulting TC0 Function Address F91H
TMOD0.2 TMOD0.1 TMOD0.0
0 1 0 0
11-17
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 11-7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings TMOD0.6 0 0 1 1 1 1 TMOD0.5 0 0 0 0 1 1 TMOD0.4 0 1 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fxx/210 (4.09 kHz) fxx /28 (16.4 kHz) fxx/26 (65.5 kHz) fxx/24 (262 kHz)
NOTE: 'fxx' = selected system clock of 4.19 MHz.
+ PROGRAMMING TIP -- Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS EMB 15 EA,#4CH TMOD0,EA IET0
2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation: BITS SMB BITS EMB 15 TMOD0.3
11-18
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero (00H). Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. The TCNT0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4). Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 reference buffer, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag, IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed.
COUNT CLOCK TREF0
~
REFERENCE VALUE = n
~
TCNT0
0
1
2
n-1
n
0
1
2
~
n-1
~ ~
n
0
1
2
3
~
MATCH TOL0
~
MATCH
~
INTERVAL TIME IRQT0 SET IRQT0 SET
TIMER START INSTRUCTION (TMOD0.3 IS SET)
Figure 11-3. TC0 Timing Diagram
~
11-19
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to 'FFH'. TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used to perform -- as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. During timer/counter operation, the value loaded into the reference register is compared to the TCNT0 value. When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0 reference register:
1 TC0 timer interval = (TREF0 value + 1) x TMOD0 frequency setting (TREF0 value 0)
TC0 OUTPUT ENABLE FLAG (TOE0) The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0 is addressable by 1-bit write instructions. (MSB) F92H "u" TOE0 "u" (LSB) "u"
NOTE: "u" means that the value is undetermined.
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. TC0 OUTPUT LATCH (TOL0) TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the value of the counter register TCNT0 and the reference value stored in the TREF0 register, the TOL0 value is inverted -- the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0 pin. Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero, along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately. When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if necessary.
11-20
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
+ PROGRAMMING TIP -- Setting a TC0 Timer Interval
To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter clock = fxx/210, and TREF0 is set to FFH): 2. Calculate the TREF0 value: 30 ms = TREF0 value + 1 4.09 kHz 30 ms 244 s = 122.9 = 7AH
TREF0 + 1 =
TREF0 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF0 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA
11-21
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
WATCH TIMER
OVERVIEW The watch timer is a multi-purpose timer which consists of three basic components: -- 8-bit watch timer mode register (WMOD) -- Clock selector -- Frequency divider circuit Watch timer functions include real-time and watch-time measurement and interval timing for the main and subsystem clock. It is also used as a clock source for the LCD controller and for generating buzzer (BUZ) output. Real-Time and Watch-Time Measurement To start watch timer operation, set bit 2 of the watch timer mode register (WMOD.2) to logic one. The watch timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. Using a System or Subsystem Clock Source The watch timer can generate interrupts based on the system clock frequency or on the subsystem clock. When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if WMOD.0 = "0", the system clock (fxx) is used as the signal source, according to the following formula: Watch timer clock (fw) = System clock (fxx) 128 = 32.768 kHz (fxx = 4.19 MHz)
This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby releasing stop mode. Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller (fLCD). Therefore, if the watch timer is disabled, the LCD controller does not operate.
11-22
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the desired BUZ frequency, load the appropriate value to the WMOD register. This output can then be used to actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met: -- The WMOD.7 register bit is set to "1" -- The output latch for I/O port 2.3 is cleared to "0" -- The port 2.3 output mode flag (PM2) set to 'output' mode Timing Tests in High-Speed Mode By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. Highspeed mode is useful for timing events for program debugging sequences. Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the input level at the XTin pin is high; if WMOD.3 is "0", the input level at the XTin pin is low.
11-23
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
P2.3 Latch WMOD.7
PM2
WMOD.6
BUZ
WMOD.5 MUX
8
WMOD.4 fw/2 (16 kHz) Enable / DISABLE WMOD.2
WMOD.3
fw/4 (8 kHz) fw/8 (4 kHz)
WMOD.1 fw/16 (2 kHz) WMOD.0
Selector Circuit
IRQ
fw/2 7
Clock Selector
fw/214 (2Hz)
fw
(32.768 kHz)
Frequency Dividing Circuit
fw/2 6 (4096 Hz)
fx = Main system clock fxt = Subsystem clock fw = Watch timer frequency fxx = System clock
fLCD
fxt
fxx/128
Figure 11-4. Watch Timer Circuit Diagram
11-24
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMERS and TIMER/COUNTERS
WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only addressable. An exception is WMOD bit 3 (the XTin input level control bit) which is 1-bit read-only addressable. A RESET automatically sets WMOD.3 to the current input level of the subsystem clock, XTin (high, if logic one; low, if logic zero), and all other WMOD bits to logic zero. F88H F89H WMOD.3 WMOD.7 WMOD.2 "0" WMOD.1 WMOD.5 WMOD.0 WMOD.4
In summary, WMOD settings control the following watch timer functions: -- Watch timer clock selection -- Watch timer speed control -- Enable/disable watch timer -- XTin input level control -- Buzzer frequency selection -- Enable/disable buzzer output (WMOD.0) (WMOD.1) (WMOD.2) (WMOD.3) (WMOD.4 and WMOD.5) (WMOD.7)
Table 11-8. Watch Timer Mode Register (WMOD) Organization Bit Name WMOD.7 Values 0 1 WMOD.6 WMOD.5-.4 0 0 1 1 WMOD.3 0 1 WMOD.2 WMOD.1 WMOD.0 0 1 0 1 0 1 0 0 1 0 1 Function Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output Always logic zero 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output Input level to XTin pin is low Input level to XTin pin is high Disable watch timer; clear frequency dividing circuits Enable watch timer Normal mode; sets IRQW to 0.5 seconds High-speed mode; sets IRQW to 3.91 ms Select fxx/128 as the watch timer clock (fw) Select subsystem clock as watch timer clock (fw) F88H Address F89H
NOTE: System clock frequency (fxx) is assumed to be 4.19 MHz; subsystem clock (fxt) is assumed to be 32.768 kHz.
11-25
TIMERS and TIMER/COUNTERS
KS57C2302/C2304/P2304 MICROCONTROLLER
+ PROGRAMMING TIP -- Using the Watch Timer
1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable: BITS SMB LD LD BITR LD LD BITS EMB 15 EA,#04H PMG2,EA P2.3 EA,#85H WMOD,EA IEW
; P2.3 output mode
2. Sample real-time clock processing method: CLOCK BTSTZ RET * * * IRQW ; 0.5 second check ; No, return ; Yes, 0.5 second interrupt generation ; Increment HOUR, MINUTE, SECOND
11-26
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
12
OVERVIEW
LCD CONTROLLER/DRIVER
The KS57C2302/C2304 microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel. Its LCD block has the following components: -- LCD controller/driver -- Display RAM for storing display data -- 32 segment output pins (SEG0-SEG31) -- 4 common output pins (COM0-COM3) -- Four LCD operating power supply pins (VLC0-VLC2) The frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings in the LCD mode register, LMOD. The LCD control register, LCON, is used to turn the LCD display on and off, to switch current to the dividing resistors for the LCD display, and to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD display expansion. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and idle modes.
3 DATA BUS LCD CONTROLLER / DRIVER
VLC0-VLC2
4
COM0-COM3
8
24
SEG0-SEG23 SEG24-SEG31/ P8.0-P8.7
8
Figure 12-1. LCD Function Diagram
12-1
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CIRCUIT DIAGRAM
1FFH.3
4
1FFH.2 1FFH.1 1FFH.0
M U X
S E L
S E G M E N
SEG31/P8.7 SEG30/P8.6 SEG29/P8.5 SEG28/P8.4 SEG27/P8.3 SEG26/P8.2 SEG25/P8.1 SEG24/P8.0 SEG23 SEG22 SEG21 SEG20 SEG19
1F4H.3
4
1F4H.2 1F4H.1 1F4H.0
M U X
S E L
T
D R I M U X V E fLCD R
1E0H.3
4
1E0H.2 1E0H.1 1E0H.0
...
SEG0 COM3 COM2 COM1 COM0 VLC0 VLC1 VLC2 LCDSY
8
LMOD
TIMING CONTROLLER
COM CONTROL
4
LCON
LCD VOLTAGE CONTROL
LCDCK
1 0 Port 3 latch
01 PMG1
Figure 12-2. LCD Circuit Diagram
12-2
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA RAM addresses of bank 1 are used as LCD data memory. These locations can be addressed by 1-bit, 4-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG31 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
1E0H 1E1H
BIT3
BIT2
BIT1
BIT0
SEG0 SEG1
. . . . . .
1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
. . . . . .
. . . . . .
. . . . . .
P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
COM3
COM2
COM1
COM0
Figure 12-3. LCD Display Data RAM Organization
Table 12-1. Common Signal Pins Used per Duty Cycle Display Mode Static 1/2 1/3 1/4 COM0 Pin Selected Selected Selected Selected COM1 Pin N/C Selected Selected Selected COM2 Pin N/C N/C Selected Selected COM3 Pin N/C N/C N/C Selected
NOTE: NC = no connection is required.
12-3
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROL REGISTER (LCON) The LCD control register (LCON) is used to turn the LCD display on and off, to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD display expansion, and to control the flow of current to dividing resistors in the LCD circuit. Following a RESET, all LCON values are cleared to "0". This turns the LCD display off and stops the flow of current to the dividing resistors. F8EH "0" LCON.2 "0" LCON.0 LCON
The effect of the LCON.0 setting is dependent upon the current setting of bits LMOD.3. Table 12-2. LCD Control Register (LCON) Organization LCON Bit LCON.3 LCON.2 LCON.1 LCON.0 Setting 0 0 1 0 0 1 Description This bit is used for internal testing only; always logic zero. Disable LCDCK and LCDSY signal outputs. Enable LCDCK and LCDSY signal outputs. Always logic zero. LCD output low, display off; cut off current to dividing resistor, and output port 8 latch contents. If LMOD.3 = "0": LCD display off; output port 8 latch contents. If LMOD.3 = "1": COM and SEG output in display mode; LCD display on.
NOTE: The LCON.3 register must be set to "0".
Table 12-3. LCON.0 and LMOD.3 Bit Settings LCON.0 LMOD.3 0 1 - 0 1 COM0-COM3 Output low; LCD display off LCD display off COM output corresponds to display mode SEG0-SEG31 P8.0-P8.7 Cut off current to dividing resistors LCD display off LCD display on
Output low; Output latch LCD display off contents LCD display off Output latch contents SEG output corresponds to display mode Output latch contents
12-4
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and display on/off. LMOD can be manipulated using 8-bit write instructions, bit 3 (LMOD.3) can be also written by 1bit instructions. F8CH F8DH LMOD.3 LMOD.7 LMOD.2 LMOD.6 LMOD.1 LMOD.5 LMOD.0 LMOD.4
The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This is also referred to as the 'frame frequency. Since LCDCK is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the LCD display is turned on. RESET clears the LMOD register values to logic zero. The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. The LCD mode register LMOD controls the output mode of the 8 pins used for normal outputs (P8.0-P8.7). Bits LMOD.7-.6 define the segment output and normal bit output configuration. Table 12-4. LCD Mode Register (LMOD) Organization LMOD.7 0 0 1 1 LMOD.5 0 0 1 1 LMOD.3 0 1 1 1 1 LMOD.6 0 1 0 1 LMOD.4 0 1 0 1 LMOD.2 - 0 0 0 0 fw/ 29 = 64 Hz fw/28 = 128 Hz fw/27 = 256 Hz fw/26 = 512 Hz LMOD.1 - 0 0 1 1 LMOD.0 - 0 1 0 1 0 Duty and Bias Selection for LCD Display LCD Display off 1/4 duty, 1/3 bias 1/3 duty, 1/3 bias 1/2 duty, 1/2 bias 1/3 duty, 1/2 bias Static LCD Output Segments and 1-Bit Output Pins Segments 24-27, and 28-31 Segments 24-27; 1-bit output at P8.4-P8.7 Segments 28-31; 1-bit output at P8.0-P8.3 1-bit output only at P8.0-P8.3 and P8.4-P8.7 LCD Clock (LCDCK) Frequency
1 1 0 NOTE: fw =32.768 kHz, watch timer clock
12-5
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 12-5. LCD Clock Signal (LCDCK), Frame Frequency and LCD sync Signal (LCDSY) LCDCK Frequency fw/29 = 64 Hz fw/28 = 128 Hz fw/27 = 256 Hz fw/26 = 512 Hz Static 64 (16) 128 (32) 256 (64) 512 (128) 1/2 Duty 32 (16) 64 (32) 128 (64) 256 (128) 1/3 Duty 21 (21) 43 (43) 85 (85) 171 (171) 1/4 Duty 16 (16) 32 (32) 64 (64) 128 (128)
NOTES: 1. fw = 32.768 kHz 2. The number in parentheses is a frequency for LCDSY.
LCD DRIVE VOLTAGE LCD Power Supply VLC0 VLC1 VLC2 VLC3 Static Mode VLCD 2/3 VLCD 1/3 VLCD 0V 1/2 Bias VLCD 1/2 VLCD 1/2 VLCD 0V 1/3 Bias VLCD 2/3 VLCD 1/3 VLCD 0V
NOTE: The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage. Therefore, always drive the LCD panel with AC voltage.
LCD VOLTAGE DIVIDING RESISTORS On-chip voltage dividing resistors for the LCD drive power supply can be configured by internal voltage dividing resistors. Using these internal voltage dividing resistors, you can drive either a 3-volt or a 5-volt LCD display using external bias. Bias pins are connected externally to the VLCD pin so that it can handle the different LCD drive voltages. To cut off the current supply to the voltage dividing resistors, clear LCON.0 when you turn the LCD display off. COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. -- In 1/2 duty mode, COM0-COM1 pins are selected -- In 1/3 duty mode, COM0-COM2 pins are selected -- In 1/4 duty mode, COM0-COM3 pins are selected SEGMENT (SEG) SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at bank 1. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
12-6
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
Static and 1/3 Bias (V LCD = 3 V at V DD = 5 V) VDD
1/2 Bias (V LCD = 2.5 V at V DD = 5 V) VDD
LCON.0
BIAS PIN 2R VLC0 R VLC1
LCON.0
BIAS PIN 2R VLC0 R VLC1
VLCD = 3 V VLC2
R R VLC3 VSS
VLCD = 2.5 V VLC2
R R VLC3 VSS
Static and 1/3 Bias (V LCD = 5 V at V DD = 5 V) Static and 1/3 Bias (V LCD = 3 V at V DD = 3 V) VDD
Voltage Dividing Resistor Adjustment VDD
LCON.0
BIAS PIN 2R VLC0 R VLC1
LCON.0
BIAS PIN 2R VLC0 R VLC1 R' R' R' VSS 2R'
VLCD = 5 V VLC2
R R VLC3 VSS
VLCD VLC2
R R VLC3
R = Voltage dividing resistor R' = External resistor
Figure 12-4. Voltage Dividing Resistor Circuit Diagrams
12-7
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
Tf VLC0 COM0 V SS VLC0 SEG11 VSS VLC0 SEG12 V SS +V LCD COM0- SEG11 0V - VLCD +V LCD COM0- SEG12 0V - VLCD
Figure 12-5. LCD Signal Waveforms in Static Mode
12-8
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
TIMING STROBE
COM3 COM2 COM1 COM0 BIT 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 X X X 0 SEG25 X X X 1 SEG26 X X X 1 SEG27 X X X 0 SEG28 X X X 0 SEG29 X X X 0 SEG30 SEG31 X X X 0 X X X 0
Open Possible
1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
X
X X X X X X X X X X X X X X X X X X X X X X X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Figure 12-6. LCD Connection Example in Static Mode
X
1
X
1
X
1
X
0
X
1
X
1
X
0
X
0
X
1
X
0
X
1
X
0
X
1
X
1
X
1
X
1
X
0
X
0
X
1
X
1
X
0
X
1
X
1
X
0
12-9
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
Tf
V LC0
COM0
V LC1, 2 VSS V LC0
COM1
V LC1, 2 V SS VLC0
SEG9
V LC1, 2 V SS + V LCD
COM0- SEG9
+ 1/2 V LCD 0 - 1/2 V LCD - V LCD
+ V LCD
COM1- SEG9
+ 1/2 V LCD 0 - 1/2 V LCD - V LCD
Figure 12-7. LCD Signal Waveforms at 1/2 Duty, 1/2 Bias
12-10
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
TIMING STROBE Bit 0 Bit 1 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH X X
COM3 COM2 COM1 COM0 SEG0 SEG1 X X 1 1 SEG2 X X 1 1 X X SEG3 SEG4 X X 1 0 X X SEG5 SEG6 X X 1 1 X X SEG7 SEG8 XX XX 1 1 0 1 SEG9 SEG10 X X 1 1 X X SEG11 SEG12 X X 1 0 X X SEG13 SEG14 XX X 1 1 X SEG15 SEG16 X X 1 0 X X SEG17 SEG18 X X 1 0 X X SEG19 SEG20 X X 1 0 SEG21 X X 1 1 X X SEG22 SEG23 X X 0 1 SEG24 X X 0 0 SEG25 X X 1 1 SEG26 X X 0 1 SEG27 X X 1 1 X X SEG28 SEG29 X X 1 0 X X 0 0 SEG30 SEG31 X X 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1
OPEN
1
Figure 12-8. LCD Connection Example at 1/2 Duty, 1/2 Bias
0
12-11
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
Tf
V LC0
COM0
V LC1, 2 V SS V LC0
COM1
V LC1, 2 V SS V LC0
COM2
V LC1, 2 V SS V LC0
SEG12
V LC1, 2 V SS + V LCD
COM0- SEG12
+ 1/2 V LCD 0 - 1/2 V LCD - V LCD + V LCD
COM1- SEG12
+ 1/2 V LCD 0 - 1/2 V LCD - V LCD + V LCD
COM2- SEG12
+ 1/2 V LCD 0 - 1/2 V LCD - V LCD
Figure 12-9. LCD Signal Waveforms at 1/3 Duty, 1/2 Bias
12-12
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
Tf
V LC0 V LC1 V LC2 VSS V LC0 V LC1 V LC2 V SS V LC0 V LC1 V LC2 V SS V LC0 V LC1 V LC2 V SS + VLCD
COM0
COM1
COM2
SEG12
COM0- SEG12
+ 1/3 VLCD 0 - 1/3 VLCD - VLCD + V LCD
COM1- SEG12
+ 1/3 V LCD 0 - 1/3 VLCD - VLCD + VLCD
COM2- SEG12
+ 1/3 V LCD 0 - 1/3 VLCD - VLCD
Figure 12-10. LCD Signal Waveforms at 1/3 Duty, 1/3 Bias
12-13
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
Timing Strobe Bit 0 Bit 1 Bit 2 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
COM3 COM2 COM1 COM0 SEG0 X 1 1 0 SEG1 X 1 0 1 SEG2 X X 1 1 SEG3 X 1 1 0 SEG4 X 1 1 1 SEG5 X X 1 0 SEG6 X 1 1 0 SEG7 X 1 1 1 SEG8 X X 1 1 SEG9 X 1 1 0 SEG10 X 1 0 0 SEG11 X X 1 0 SEG12 X 0 1 1 SEG13 X 1 1 1 SEG14 X X 1 1 SEG15 X 0 1 0 SEG16 X 1 1 1 SEG17 X X 1 0 SEG18 X 1 1 0 SEG19 X 0 1 0 SEG20 X X 1 0 SEG21 X 1 1 0 SEG22 X 1 1 1 SEG23 X X 0 0 SEG24 X 1 0 0 SEG25 X 1 1 1 SEG26 SEG27 X 1 1 0 SEG28 X 0 0 0 SEG29 X X 0 0 X X 0 1
OPEN
X
X
X X
X
X
Figure 12-11. LCD Connection Example at 1/3 Duty, 1/3 Bias
12-14
X
X
KS57C2302/C2304/P2304 MICROCONTROLLER
LCD CONTROLLER/DRIVER
Tf
VLC0 V LC1 V LC2 V SS VLC0 V LC1 V LC2 V SS VLC0 V LC1 V LC2 V SS VLC0 V LC1 V LC2 V SS VLC0 V LC1 V LC2 V SS + V LCD + 1/3 V LCD 0 - 1/3 V LCD - V LCD + V LCD + 1/3 V LCD
COM0
COM1
COM2
COM3
SEG13
COM0- SEG13
COM1- SEG13
0 - 1/3 VLCD - V LCD
Figure 12-12. LCD Signal Waveforms at 1/4 Duty, 1/3 Bias
12-15
LCD CONTROLLER/DRIVER
KS57C2302/C2304/P2304 MICROCONTROLLER
Timing Strobe Bit 0 Bit 1 Bit 2 Bit 3 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
COM3 COM2 COM1 COM0 SEG0 1 0 1 0 SEG1 1 1 1 1 SEG2 1 0 1 0 SEG3 1 1 0 1 SEG4 0 1 1 0 1 1 0 SEG5 0 SEG6 1 1 1 0 SEG7 0 1 0 1 SEG8 1 1 0 0 SEG9 0 1 1 1 SEG10 0 1 1 0 SEG11 0 0 0 0 SEG12 1 1 1 0 SEG13 1 0 1 1 SEG14 1 1 1 0 SEG15 1 1 0 1 SEG16 1 1 1 0 SEG17 1 1 1 1 SEG18 1 1 1 0 SEG19 1 0 0 0 1 0 1 0 SEG20 SEG21 1 1 1 1 SEG22 1 0 1 0 SEG23 1 1 0 1 SEG24 0 1 1 0 SEG25 1 1 0 0 SEG26 SEG27 0 1 0 1 SEG28 1 1 0 0 SEG29 SEG30 0 1 1 0 SEG31 0 0 0 0 0 1 1 1 1 1 1 0
Figure 12-13. LCD Connection Example at 1/4 Duty, 1/3 Bias
12-16
KS57C2302/C2304/P2304 MICROCONTROLLER
ELECTRICAL DATA
13
OVERVIEW
-- I/O capacitance
ELECTRICAL DATA
In this section, information on KS57C2302/C2304 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL0 timing -- Input timing for RESET -- Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 13-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL One I/O port active All I/O ports active Output Current Low One I/O port active All I/O ports Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 (note) Total value for ports 2 and 3 Total value for port 6 Operating Temperature Storage Temperature TA Tstg - - + 60 (Peak value) + 20 + 50 + 20
(note) (note)
Units V
mA
- 40 to + 85 - 65 to + 150
Duty .
C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 13-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below for VIH2, VIH3 Ports 1, 6, and RESET XIN, XOUT, and XTIN Ports 2 and 3 Ports 1, 6 and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 2, 3, 6 and BIAS VDD = 4.5 V to 5.5 V IOH = -100 A Port 8 only Min 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 Typ - - - - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V
VOH2
VDD - 2.0
-
-
13-2
KS57C2302/C2304/P2304 MICROCONTROLLER
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output low voltage Symbol VOL1 VOL2 Input high leakage current ILIH1 Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 2, 3, 6 VDD = 4.5 V to 5.5 V IOL = 100 A; Port 8 only VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT and XTIN VIN = 0 V All input pins except XIN, XOUT, and XTIN VIN = 0 V XIN, XOUT, and XTIN VOUT = VDD All output pins VOUT = 0 V All output pins VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V
RESET
Min - - -
Typ 0.4 - -
Max 2 1 3
Units V
A
ILIH2 Input low leakage current ILIL1
20 - - -3
ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH1
- 20 - - 3 A
ILOL
-3
RL1
25 50 100 200 100
50 100 250 500 150
100 200 400 800 200
K
VDD = 3 V LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation VDC RSEG RLCD TA = 25 oC VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) Io = 15uA (i= 0-3)
RCOM
-
3 5 3 5 45
6 15 6 15 90 mV
-
13-3
ELECTRICAL DATA
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 13-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter SEG output voltage deviation VLC0 Output voltage VLC1 Output voltage VLC2 Output voltage VLC1 VLC2 TA = 25 oC TA = 25 oC Symbol VDS Conditions VDD = 5 V (VLC0-SEGi) Io = 15uA (i= 0-31) VLC0 TA = 25 oC 0.6VDD - 0.2 0.4VDD - 0.2 0.2VDD - 0.2 0.6VDD 0.4VDD 0.2VDD 0.6VDD + 0.2 0.4VDD + 0.2 0.2VDD + 0.2 V Min - Typ n 45 Max n 90 Units mV
13-4
KS57C2302/C2304/P2304 MICROCONTROLLER
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1
(2)
Conditions Main operating: VDD = 5 V 10% CPU = fx/4 SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10%
Min 6.0 MHz 4.19 MHz -
Typ 3.5 2.5
Max 8 5.5
Units mA
6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz -
1.6 1.2 1 0.9
4 3 2.5 2
IDD2 (2)
Main idle mode; VDD = 5 V 10% CPU = fx/4 SCMOD =0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10%
6.0 MHz 4.19 MHz -
0.5 0.4 15
1.0 0.8 30 A
IDD3
IDD4
Sub operating: VDD = 3 V 10% CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Sub idle mode: VDD = 3 V 10% CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Stop mode: VDD = 5V 10% CPU=fxt/4, SCMOD = 1101B Stop mode: VDD = 5 V 10% CPU = fx/4, SCMOD = 0100B
-
6
15
IDD5
IDD6 (3)
-
0.5
3
NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors and through LCD voltage dividing resistors. 2. Data includes the power consumption for sub-system clock oscillation. 3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The mainsystem clock oscillation stops by the STOP instruction.
13-5
ELECTRICAL DATA
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 13-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
(1)
Parameter Oscillation frequency
Test Condition -
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range. -
-
-
4
ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency
(1)
0.4
-
6.0
MHz
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V
- - 0.4
- - -
10 30 6.0
ms
External Clock
XIN
XOUT
XIN input frequency (1)
-
MHz
XIN input high and low level width (tXH, tXL) RC Oscillator
XIN XOUT R
- VDD = 5 V R = 20 K, VDD = 5 V R = 39 K, VDD = 3 V
83.3 0.4
- - 2.0 1.0
- 2
ns MHz
Frequency (1)
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
13-6
KS57C2302/C2304/P2304 MICROCONTROLLER
ELECTRICAL DATA
Table 13-4. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
(1)
Parameter Oscillation frequency
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V VDD = 1.8 V to 4.5 V
- - 32
1.0 - -
2 10 100
s
External Clock
XTIN XTOUT
XTIN input frequency
(1)
-
KHz
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
Table 13-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
13-7
ELECTRICAL DATA
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 13-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction cycle time (1) TCL0 input frequency TCL0 input high, low width Interrupt input high, low width
RESET
Symbol tCY
Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt)
Min 0.67 0.95 114 0
Typ - - 122 -
Max 64 64 125 1.5 1
Units s
f TI0 tTIH0, tTIL0 tINTH, tINTL tRSL
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V INT0 INT1, INT2, KS0-KS3 Input
MHz MHz s s s
0.48 1.8
(2)
-
-
-
-
10 10 - -
Input Low
Width
NOTES: 1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source. 2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
13-8
KS57C2302/C2304/P2304 MICROCONTROLLER
ELECTRICAL DATA
CPU CLOCK 1.5 MHz 1.0475 MHz 750 kHz 500 kHz 250 kHz
Main OSC. Freq. 6 MHz 4.19 MHz 3 MHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range Table 13-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions Normal operation VDDDR = 2.0 V Normal operation Released by RESET Released by interrupt Min 1.5 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 6.5 1 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-9
ELECTRICAL DATA
KS57C2302/C2304/P2304 MICROCONTROLLER
TIMING WAVEFORMS
INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
RESET
tWAIT t SREL
Figure 13-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
tSREL
POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST)
t WAIT
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
13-10
KS57C2302/C2304/P2304 MICROCONTROLLER
ELECTRICAL DATA
0.8 VDD 0.2 VDD
MEASUREMENT POINTS
0.8 VDD 0.2 VDD
Figure 13-4. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / fx
tXL
t XH
Xin
VDD - 0.1 V
0.1 V
Figure 13-5. Clock Timing Measurement at Xin
1 / fxt
t XTL
t XTH
XTin
VDD - 0.1 V
0.1 V
Figure 13-6. Clock Timing Measurement at XTin
13-11
ELECTRICAL DATA
KS57C2302/C2304/P2304 MICROCONTROLLER
1 / f TI0
t TIL0
t TIH0
TCL0
0.8 V DD 0.2 V DD
Figure 13-7. TCL0 Timing
tRSL
RESET
0.2 VDD
Figure 13-8. Input Timing for RESET Signal
tINTL
t INTH
INT0, 1, 2, 4 KS0 to KS3
0.8 VDD 0.2 VDD
Figure 13-9. Input Timing for External Interrupts and Quasi-Interrupts
13-12
KS57C2302//C2304/P2304 MICROCONTROLLER
MECHANICAL DATA
14
OVERVIEW
MECHANICAL DATA
The KS57C2302/C2304 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F). Package dimensions are shown in Figure 14-1.
23.90 0.3 20.00 0.2
0-8 0.15
+0.10 - 0.05
17.90 0.3
14.00 0.2
64-QFP-1420F
0.80 0.20 #1 1.00 0.40 - 0.05 0.15MAX
+0.10
0.10 MAX
#64 (1.00 )
0.05~0.25 (1.00) 2.65 0.10 3.00 MAX
0.80 0.20 NOTE: Dimensions are in millimeters.
Figure 15-1. 64-QFP-1420F Package Dimensions
14-1
MECHANICAL DATA
KS57C2302//C2304/P2304 MICROCONTROLLER
NOTES
14-2
KS57C2302/C2304/P2304 MICROCONTROLLER
KS57P2304 OTP
15
OVERVIEW
KS57P2304 OTP
The KS57P2304 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C2302/C2304 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The KS57P2304 is fully compatible with the KS57C2302/C2304, both in function and in pin configuration. Because of its simple programming requirements, the KS57P2304 is ideal for use as an evaluation chip for the KS57C2304.
15-1
KS57P2304 OTP
KS57C2302/C2304/P2304 MICROCONTROLLER
COM0 COM1 COM2 COM3 BIAS VLC0 SDAT /VLC1 SCLK /VLC2 VDD /VDD VSS/VSS Xout Xin VPP/TEST XTin XTout
RESET / RESET
P1.0/INT0 P1.1/INT1 P1.2/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12
KS57P2304
(TOP VIEW)
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P8.0 SEG25/P8.1 SEG26/P8.2 SEG27/P8.3 SEG28/P8.4 SEG29/P8.5 SEG30/P8.6 SEG31/P8.7
Figure 15-1. KS57P2304 Pin Assignments (64-QFP)
15-2
P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 P3.3 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3
20 21 22 23 24 25 26 27 28 29 30 31 32
KS57C2302/C2304/P2304 MICROCONTROLLER
KS57P2304 OTP
Table 15-1. Pin Descriptions Used to Read/Write the EPROM Main Chip Pin Name VLC1 Pin Name SDAT Pin No. 7 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
VLC2 TEST
SCLK VPP (TEST)
8 13
I/O I
RESET
RESET
16 9/10
I I
VDD / VSS
VDD / VSS
Table 15-2. Comparison of KS57P2304 and KS57C2302/C2304 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS57P2304 4-Kbyte EPROM 2.0 V to 5.5 V at 4.19 MHz 1.8 V to 5.5 V at 3 MHz VDD = 5 V, VPP (TEST) = 12.5 V 64 QFP User Program 1 time 64 QFP Programmed at the factory KS57C2302/C2304 2-K / 4-Kbyte mask ROM 2.0 V to 5.5 V at 4.19 MHz 1.8 V to 5.5 V at 3 MHz -
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the Vpp (TEST) pin of the KS57P2304, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V Vpp (TEST) 5V 12.5 V 12.5 V 12.5 V REG/
MEM
Address (A15-A0) 0000H 0000H 0000H 0E3FH
R/W 1 0 1 0 EPROM read
Mode
0 0 0 1
EPROM program EPROM verify EPROM read protection
NOTE: "0" means low level; "1" means high level.
15-3
KS57P2304 OTP
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 15-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH1 Conditions All input pins except those specified below for VIH2, VIH3 Ports 1, 6, and RESET XIN, XOUT, and XTIN Ports 2 and 3 Ports 1, 6 and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 2, 3, 6 and BIAS VDD = 4.5 V to 5.5 V IOH = -100 A Port 8 only VDD = 4.5 V to 5.5 V IOL = 15 mA, Ports 2, 3, 6 VDD = 4.5 V to 5.5 V IOL = 100 A; Port 8 only VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT and XTIN VIN = 0 V All input pins except XIN, XOUT, and XTIN VIN = 0 V XIN, XOUT, and XTIN VOUT = VDD All output pins VOUT = 0 V All output pins Min 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 Typ - - - - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V
VOH2 Output low voltage VOL1 VOL2 Input high leakage current ILIH1
VDD - 2.0 - - -
- 0.4 - -
- 2 1 3 A V
ILIH2 Input low leakage current ILIL1
- -
- -
20 -3 A
ILIL2 Output high leakage current Output low leakage current ILOH1
- -
- -
- 20 3 A
ILOL
-
-
-3
15-4
KS57C2302/C2304/P2304 MICROCONTROLLER
KS57P2304 OTP
Table 15-4. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Pull-up resistor Symbol RL1 Conditions VIN = 0 V; VDD = 5 V Ports 1, 2, 3, 6 VDD = 3 V RL2 VIN = 0 V; VDD = 5 V
RESET
Min 25 50 100
Typ 50 100 250
Max 100 200 400
Units K
VDD = 3 V LCD voltage dividing resistor COM output impedance SEG output impedance COM output voltage deviation SEG output voltage deviation VLC0 Output voltage VLC1 Output voltage VLC2 Output voltage VLC1 VLC2 TA = 25 oC TA = 25 oC VDC RSEG RLCD TA = 25 oC VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V (VLC0-COMi) Io = 15uA (i= 0-3) VDS VDD = 5 V (VLC0-SEGi) Io = 15uA (i= 0-31) VLC0 TA = 25 oC
200 100
500 150
800 200
RCOM
-
3 5 3 5
6 15 6 15 90 mV
-
45
-
n 45
n 90
mV
0.6VDD - 0.2 0.4VDD - 0.2 0.2VDD - 0.2
0.6VDD 0.4VDD 0.2VDD
0.6VDD + 0.2 0.4VDD + 0.2 0.2VDD + 0.2
V
15-5
KS57P2304 OTP
KS57C2302/C2304/P2304 MICROCONTROLLER
Table 15-4. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1
(2)
Conditions Main operating: VDD = 5 V 10% CPU = fx/4 SCMOD = 0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10%
Min 6.0 MHz 4.19 MHz -
Typ 3.5 2.5
Max 8 5.5
Units mA
6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz -
1.6 1.2 1 0.9
4 3 2.5 2
IDD2 (2)
Main idle mode; VDD = 5 V 10% CPU = fx/4 SCMOD =0000B Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10%
6.0 MHz 4.19 MHz -
0.5 0.4 15
1.0 0.8 30 A
IDD3
IDD4
Sub operating: VDD = 3 V 10% CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Sub idle mode: VDD = 3 V 10% CPU = fxt/4, SCMOD = 1001B 32 kHz crystal oscillator Stop mode: VDD = 5V 10% CPU=fxt/4, SCMOD = 1101B Stop mode: VDD = 5 V 10% CPU = fx/4, SCMOD = 0100B
-
6
15
IDD5
IDD6 (3)
-
0.5
3
NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors 2. 3. and through LCD voltage dividing resistors. Data includes the power consumption for sub-system clock oscillation. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The mainsystem clock oscillation stops by the STOP instruction.
15-6
KS57C2302/C2304/P2304 MICROCONTROLLER
KS57P2304 OTP
CPU CLOCK 1.5 MHz 1.0475 MHz 750 kHz 500 kHz 250 kHz
Main OSC. Freq. 6 MHz 4.19 MHz 3 MHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 15-2. Standard Operating Voltage Range
15-7
KS57P2304 OTP
KS57C2302/C2304/P2304 MICROCONTROLLER
I OL (mA)
35.00 VDD = 5.5 V
VDD = 4.5 V 3.500/div
VDD = 3.3 V
VDD = 2.2 V
.0000 .0000
.2000/div
2.000 VOL (V)
Figure 15-3. Port 2 IOL vs VOL Curve
15-8
KS57C2302//C2304/P2304 MICROCONTROLLER
DEVELOPMENT TOOLS
16
OVERVIEW SHINE
Development Tools
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM57 The SASM57 is an relocatable assembler for Samsung's KS57-series microcontrollers. The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all KS57-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. OTPs One time programmable microcontroller (OTP) for the KS57C2302/C2304 microcontroller and OTP programmer (Gang) are now available.
16-1
DEVELOPMENT TOOLS
KS57C2302//C2304/P2304 MICROCONTROLLER
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/MTP WRITER UNIT
TARGET APPLICATION SYSTEM
RAM BREAK/ DISPLAY UNIT PROBE ADAPTER BUS TRACE/TIMER UNIT
POD SAM4 BASE UNIT
TB572302A/04A TARGET BOARD
POWER SUPPLY UNIT
EVA CHIP
Figure 16-1. SMDS Product Configuration (SMDS2+)
16-2
KS57C2302//C2304/P2304 MICROCONTROLLER
DEVELOPMENT TOOLS
TB572302A/04A TARGET BOARD The TB572302A/04A target board is used for the KS57C2302/C2304/P2304 microcontroller. It is supported by the SMDS2+ development system.
TB572302A/04A
To User_Vcc OFF ON
BIAS VLC0 VLC1 VLC2
RESET
IDLE
STOP
74HC11
+
+
25 J101 100-PIN CONNECTOR J102
1
2
1
2
40-PIN CONNECTOR
1
1
XI XTI
3
XTAL
XTAL
MDS
EXTERNAL TRIGGERS CH1 CH2
MDS
39
40 39
40-PIN CONNECTOR
40
144 QFP KS57E2304 EVA CHIP
SM1256A
Figure 16-2. TB572302A/04A Target Board Configuration
16-3
DEVELOPMENT TOOLS
KS57C2302//C2304/P2304 MICROCONTROLLER
Table 16-1. Power Selection Settings for TB572302A/04A 'To User_Vcc' Settings To User_Vcc OFF ON
TB572302A /04A TARGET SYSTEM
Operating Mode
Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system.
VCC VSS
VCC SMDS2/SMDS2+
To User_Vcc OFF ON
TB572302A /04A External VCC VSS VCC SMDS2/SMDS2+ TARGET SYSTEM
The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
Table 16-2. Main-clock Selection Settings for TB572302A/04A Main Clock Setting XI XTAL MDS Operating Mode
EVA CHIP KS57E2304 XOUT No connection 100 pin connector
Comments Set the XI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
XIN
SMDS2/SMDS2+
XI XTAL MDS
EVA CHIP KS57E2304 XOUT XTAL TARGET BOARD
Set the XI switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XIN
16-4
KS57C2302//C2304/P2304 MICROCONTROLLER
DEVELOPMENT TOOLS
Table 16-3. Sub-clock Selection Settings for TB572302A/04A Sub Clock Setting XTI XTAL MDS Operating Mode
EVA CHIP KS57E2304 XOUT No connection 100 pin connector
Comments Set the XTI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
XIN
SMDS2/SMDS2+
XTI XTAL MDS
EVA CHIP KS57E2304 XTOUT XTAL TARGET BOARD
Set the XTI switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XTIN
Table 16-4. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from external trigger sources of the application system
EXTERNAL TRIGGERS CH1 CH2
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. IDLE LED This LED is ON when the evaluation chip (KS57E2304) is in idle mode. STOP LED This LED is ON when the evaluation chip (KS57E2304) is in stop mode.
16-5
DEVELOPMENT TOOLS
KS57C2302//C2304/P2304 MICROCONTROLLER
J101
COM0 COM2 BIAS VLC1 VDD Xout TEST XTout P1.0/INT0 P1.2/INT2 P2.0/TCLO0 P2.2/CLO P3.0/LCDCK P3.2 P6.0/KS0 P6.2/KS2 NC NC NC NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 COM1 COM3 VLC0 VLC2 VSS Xin XTin
RESET
J102
P8.7/SEG31 P8.5/SEG29 P8.3/SEG27 P8.1/SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 SEG3 SEG1 NC NC NC NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P8.6/SEG30 P8.4/SEG28 P8.2/SEG26 P8.0/SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 SEG2 SEG0 NC NC NC NC
Figure 16-3. 40-Pin Connectors for TB572302A/04A
TARGET BOARD J101 1 2 J102 1 2 40-PIN DIP CONNECTOR
40-PIN DIP CONNECTOR
40-PIN DIP CONNECTOR
P1.1/INT1 P1.3/TCL0 P2.1 P2.3/BUZ P3.1/LCDSY P3.3 P6.1/KS1 P6.3/KS3 NC NC NC NC
TARGET SYSTEM J102 1 2 J101 1 2
Target Cable for 40 Pin Connector Part Name: AS40D-A Order Code: SM6306
39 40 39 40 39 40 39 40
Figure 16-4. TB572302A/04A Adapter Cable for 64-QFP Package (KS57C2302/C2304/P2304)
16-6
KS57 SERIES MASK ROM ORDER FORM
Product description: Device Number: KS57C__________- ___________(write down the ROM code number) Product Order Form: Package Pellet Wafer Package Type: __________
Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form
+
For what kind of product will you be using this order? New product Replacement of an existing product Upgrade of an existing product Other
If you are replacing an existing product, please indicate the former product name ( )
+
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Mask Charge (US$ / Won): Customer Information: Company Name: Signatures:
____________________________
___________________ ________________________ (Person placing the order)
Telephone number
_________________________
__________________________________ (Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS57 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: KS57C________- ________ (write down the ROM code number) Number of Pins: ____________ Package Type: _____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________
________________________________________________________________ ________________________________________________________________
Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS
Signatures:
_______________________________ (Person Placing the Risk Order)
_______________________________________ (SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS57C2302 MASK OPTION SELECTION FORM
Device Number: KS57C2302-__________(write down the ROM code number)
Attachment (Check one):
Diskette
PROM
Customer Checksum:
________________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Please answer the following questions:
+
Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation
Please describe in detail its application
___________________________________________________________________________
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS57C2304 MASK OPTION SELECTION FORM
Device Number: KS57C2304-__________(write down the ROM code number)
Attachment (Check one):
Diskette
PROM
Customer Checksum:
________________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Please answer the following questions:
+
Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation
Please describe in detail its application
___________________________________________________________________________
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS57 SERIES OTP FACTORY WRITING ORDER FORM (1/2)
Product Description: Device Number: KS57P______-________(write down the ROM code number) Package Package Type: Pellet _____________________ Wafer Product Order Form: If the product order form is package: Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity: ROM Code Release Date Required Delivery Date of Device Quantity
Please answer the following questions:
+
What is the purpose of this order? New product development Replacement of an existing microcontroller Upgrade of an existing product Other
If you are replacing an existing microcontroller, please indicate the former microcontroller name ( )
+
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Customer Information: Company Name: Signatures: ___________________ ________________________ (Person placing the order) Telephone number _________________________
__________________________________ (Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS57P2304 OTP FACTORY WRITING ORDER FORM (2/2)
Device Number: KS57P2304-__________(write down the ROM code number)
Customer Checksums:
_______________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Read Protection(1):
Yes
No
Please answer the following questions: + Are you going to continue ordering this device? Yes If so, how much will you be ordering? No _________________pcs
+
Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation
Please describe in detail its application
___________________________________________________________________________
NOTES 1. Once you choose a read protection, you cannot read again the programming code from the EPROM. 2. OTP Writing will be executed in our manufacturing site. 3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

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